公开(公告)号：US20210408035A1

公开(公告)日：2021-12-30

申请号：US17038870

申请日：2020-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jo SATO ,  Kota FUNAYAMA ,  Tatsuya HINOUE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20220181343A1

公开(公告)日：2022-06-09

申请号：US17113254

申请日：2020-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Masanori TSUTSUMI ,  Kota FUNAYAMA

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11526

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located between a drain-side dielectric layer and a source-side dielectric layer. Memory openings vertically extend through the alternating stack. Each of the memory openings has a greater lateral dimension an interface with the source-side dielectric layer than at an interface with the drain-side dielectric layer. Memory opening fill structures are located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a vertical stack of memory elements, and a drain region. A logic die may be bonded to a source-side dielectric layer side of the memory die.

公开(公告)号：US20170236896A1

公开(公告)日：2017-08-17

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhenyu LU ,  Kota FUNAYAMA ,  Chun-Ming WANG ,  Jixin YU ,  Chenche HUANG ,  Tong ZHANG ,  Daxin MAO ,  Johann ALSMEIER ,  Makoto YOSHIDA ,  Lauren MATSUMOTO

IPC: H01L29/06 ,  H01L27/115

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.

公开(公告)号：US20200006373A1

公开(公告)日：2020-01-02

申请号：US16019677

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO ,  Koji MIYATA ,  Kota FUNAYAMA

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/768

Abstract: A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

公开(公告)号：US20240196610A1

公开(公告)日：2024-06-13

申请号：US18350595

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryoichi EHARA ,  Kenji SUGIURA ,  Katsufumi OKAMOTO ,  Yudai TANAKA ,  Kota FUNAYAMA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A memory device is formed by forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming an access trench through a portion of the alternating stack forming an access trench fill structure in the access cavity, and iteratively performing multiple instances of a unit processing sequence. Each instance of the unit processing sequence includes a vertical recess etch step that vertically recesses the access trench fill structure and an isotropic etch step that isotropically recesses the sacrificial material layers. A finned access cavity is formed after the multiple instances of the unit processing sequence. A finned dielectric support structure is formed in the finned access cavity, and the sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20230275026A1

公开(公告)日：2023-08-31

申请号：US17682515

申请日：2022-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Kota FUNAYAMA

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.

公开(公告)号：US20230240070A1

公开(公告)日：2023-07-27

申请号：US17583456

申请日：2022-01-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kota FUNAYAMA ,  Satoshi SHIMIZU ,  Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.

公开(公告)号：US20210210428A1

公开(公告)日：2021-07-08

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto OHSAWA ,  Kota FUNAYAMA ,  Hisaya SAKAI ,  Yoshitaka OTSU

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

公开(公告)号：US20210005627A1

公开(公告)日：2021-01-07

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Kengo KAJIWARA ,  Ryosuke ITOU ,  Naohiro HOSODA ,  Yohei MASAMORI ,  Kota FUNAYAMA ,  Keisuke TSUKAMOTO ,  Hirofumi WATATANI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

公开(公告)号：US20180130812A1

公开(公告)日：2018-05-10

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Takeshi KAWAMURA ,  Yoko FURIHATA ,  Kota FUNAYAMA

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.