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    SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, DATA PROCESSING SYSTEM, AND CONTROL SYSTEM OF THE SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, DATA PROCESSING SYSTEM, AND CONTROL SYSTEM OF THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250029648A1

    公开(公告)日：2025-01-23

    申请号：US18715300

    申请日：2022-12-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Masashi FUJITA ,  Kazuaki OHSHIMA

    IPC: G11C11/405 ,  H10B12/00

    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a register. The register includes a flip-flop and a plurality of data retention circuits. The flip-flop includes a first transistor in which a semiconductor layer including a channel formation region is silicon, an input terminal of the flip-flop is electrically connected to each of output terminals of the data retention circuits, and an output terminal of the flip-flop is electrically connected to each of input terminals of the data retention circuits. The data retention circuits include a second transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor, and when the second transistor is in a non-conduction state, the data retention circuits have a function of retaining a potential corresponding to data corresponding to a plurality of tasks. A state control portion rewrites data that the flip-flop has on the basis of data retained in the data retention circuits in accordance with the plurality of tasks executed by a processor core.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230284429A1

    公开(公告)日：2023-09-07

    申请号：US18016745

    申请日：2021-07-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiromichi GODO ,  Kazuki TSUDA ,  Yoshiyuki KUROKAWA ,  Satoru OHSHITA ,  Takuro KANEMURA ,  Hidefumi RIKIMARU

    IPC: H10B12/00 ,  G11C11/405 ,  G11C11/54

    CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/54

    Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor. The output current is current flowing when the third transistor operates in a subthreshold region.

    Control Circuit Of Secondary Battery And Electronic Device
    7.
    发明公开
    Control Circuit Of Secondary Battery And Electronic Device 审中-公开

    公开(公告)号：US20230273637A1

    公开(公告)日：2023-08-31

    申请号：US18024198

    申请日：2021-08-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Takuro KANEMURA ,  Hidefumi RIKIMARU ,  Takayuki IKEDA ,  Yuto YAKUBO ,  Shunpei YAMAZAKI

    IPC: G05F3/24 ,  H01M10/42

    CPC classification number: G05F3/24 ,  H01M10/425

    Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes. The third capacitor retains a voltage applied to the back gate by being applied with a voltage for polarization inversion in the ferroelectric layer.

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权

    公开(公告)号：US20230049977A1

    公开(公告)日：2023-02-16

    申请号：US17785510

    申请日：2020-12-14

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

    IPC: G06N3/063 ,  G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G06F7/544

    Abstract: A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.

    IMAGING DEVICE
    9.
    发明申请
    IMAGING DEVICE 有权

    公开(公告)号：US20220077205A1

    公开(公告)日：2022-03-10

    申请号：US17517705

    申请日：2021-11-03

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA ,  Hiroki INOUE ,  Takuro OHMARU

    IPC: H01L27/146 ,  H01L21/8234 ,  H04N5/225 ,  H01L27/12 ,  H01L27/088 ,  H01L29/786 ,  H01L31/075

    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

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