公开(公告)号：US20190035740A1

公开(公告)日：2019-01-31

申请号：US16048108

申请日：2018-07-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Samuele SCIARRILLO ,  Paolo COLPANI ,  Ivan VENEGONI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/525 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/53238 ,  H01L21/76852 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03005 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05566 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2924/01014 ,  H01L2924/14

Abstract: A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

公开(公告)号：US20200051935A1

公开(公告)日：2020-02-13

申请号：US16535029

申请日：2019-08-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Michele MOLGG ,  Cosimo CIMINELLI ,  Paolo COLPANI ,  Samuele SCIARRILLO ,  Ivan VENEGONI ,  Francesco Maria PIPIA ,  Simone BOSSI ,  Carmela CUPETA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

公开(公告)号：US20240088012A1

公开(公告)日：2024-03-14

申请号：US17941886

申请日：2022-09-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Francesca MILANESI ,  Paolo COLPANI

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49861 ,  H01L21/76834

Abstract: The present disclosure is directed to embodiments of a conductive structure on a conductive layer, which may be a conductive damascene layer of a semiconductor device or package. The conductive damascene layer may be within a substrate of the semiconductor device or package. A crevice is present between one or more sidewalls of the conductive structure and one or more sidewalls of one or more insulating layers on the substrate and extends to a surface of the conductive layer. A sealing layer is formed in the crevice that seals the conductive layer from moisture and contaminants external to the semiconductor device or package that may enter the crevice. In other words, the sealing layer stops the moisture and contaminants from reaching the conductive layer such that the conductive layer does not corrode due to exposure to the moisture and contaminants.

公开(公告)号：US20230005848A1

公开(公告)日：2023-01-05

申请号：US17944983

申请日：2022-09-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Paolo COLPANI ,  Samuele SCIARRILLO ,  Ivan VENEGONI ,  Francesco Maria PIPIA ,  Simone BOSSI ,  Carmela CUPETA

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

公开(公告)号：US20230187389A1

公开(公告)日：2023-06-15

申请号：US18078561

申请日：2022-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Samuele SCIARRILLO ,  Paolo COLPANI

IPC: H01L23/00 ,  C23C16/455 ,  C23C16/50 ,  C23C16/40 ,  C23C16/56 ,  C23C16/34 ,  G01R31/28 ,  H01L23/31 ,  H01L23/29 ,  H01L21/66

CPC classification number: H01L24/02 ,  C23C16/45536 ,  C23C16/50 ,  C23C16/403 ,  C23C16/405 ,  C23C16/56 ,  C23C16/34 ,  G01R31/2886 ,  H01L23/3192 ,  H01L23/291 ,  H01L22/14 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2924/0132 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/01029

Abstract: To manufacture a redistribution layer for an integrated circuit, a first insulating layer is formed on a conductive interconnection layer of a wafer. A conductive body is then formed in electrical contact with the interconnection layer. The conductive body is then covered with an insulating region having an aperture that exposes a surface of the conductive body. The surface of the conductive body and the insulating region are then covered with an insulating protection layer having a thickness less than 100 nm. This insulating protection layer is configured to provide a protection against oxidation and/or corrosion of the conductive body.

公开(公告)号：US20220384371A1

公开(公告)日：2022-12-01

申请号：US17750954

申请日：2022-05-23

Applicant: STMicroelectronics S.r.l.

Inventor： Samuele SCIARRILLO ,  Paolo COLPANI

IPC: H01L23/00

Abstract: A redistribution layer for an integrated circuit is made by forming a conductive interconnection layer; forming a conductive body in electrical contract with the interconnection layer; and covering the conductive body with a first coating layer having a thickness less than 100 nm. The first coating layer is configured to provide a protection against oxidation and/or corrosion of the conductive body. To carry out an electrical test of the integrated circuit, a testing probe locally perforates the first coating layer until the conductive body is electrically contacted by the testing probe.

公开(公告)号：US20190035741A1

公开(公告)日：2019-01-31

申请号：US16048123

申请日：2018-07-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Samuele SCIARRILLO ,  Ivan VENEGONI ,  Paolo COLPANI ,  Francesca MILANESI

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01L21/308

Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.