公开(公告)号：US20040181643A1

公开(公告)日：2004-09-16

申请号：US10735250

申请日：2003-12-12

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G06F013/00

CPC classification number: G11C7/1051 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1063 ,  G11C7/22 ,  G11C16/32

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract translation: 一种存储器系统，包括用于存储数字数据的半导体存储器，所述存储器可连接到控制装置，以便接收地址信号并且通过输出可用地址信号选择数据。 该系统的特征在于，其包括用于在读取操作期间激活等待信号以发送到控制设备的发生电路，以便指示要读取的数据的不可用性。 发生电路是这样的，以等待信号去激活，以便在与所述存储器的有效访问时间相关的等待时间间隔之后，指示待读取的数据的可用性。

公开(公告)号：US20030133325A1

公开(公告)日：2003-07-17

申请号：US10340207

申请日：2003-01-10

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Silvagni ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C16/08 ,  G11C2216/22

Abstract: A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

Abstract translation: 存储器件包括组织成多个扇区的存储器单元的阵列，并且本地字线和本地位线连接到每个相应扇区中的存储器单元。 主读取字线和主程序字线连接到每个扇区中的本地字线。 主读取行解码器连接到主读取字线，连接到主程序字线的主程序行解码器。 主读位线和主程序位线连接到每个扇区中的本地位线。 主读取列解码器连接到主读取位线，主程序列解码器连接到主程序字线。 读地址总线连接到主读行解码器和主读列解码器，以提供地址。 程序地址总线连接到主读取列解码器和主程序行解码器，以向其提供地址。

公开(公告)号：US20040170061A1

公开(公告)日：2004-09-02

申请号：US10729829

申请日：2003-12-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G11C011/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454

Abstract: A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1-MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second programming pulse to those memory cells in the group whose programming state is not ascertained to correspond to a desired programming state. A voltage applied to a control electrode of the memory cells is varied between the at least one first programming pulse and the at least one second programming pulse according to a forecasted change in biasing conditions of the memory cells in the group between said at least one first and at least one second programming pulses. Undesired over-programming of the memory cells is thus avoided.

Abstract translation: 用于对电可编程存储器进行编程的装置和方法将至少一个第一编程脉冲施加到存储器的一组存储器单元（MC1-MCK），访问该组的存储单元以确定其编程状态，并且至少应用 对于编程状态未被确定以对应于期望的编程状态的组中的那些存储器单元的一秒编程脉冲。 根据在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间的所述组中的存储器单元的偏置条件的预测变化，施加到所述存储器单元的控制电极的电压在所述至少一个第一编程脉冲和所述至少一个第二编程脉冲之间变化 和至少一个第二编程脉冲。 因此避免了对存储器单元的不期望​​的过度编程。

公开(公告)号：US20020196171A1

公开(公告)日：2002-12-26

申请号：US10060076

申请日：2002-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Osama Khouri ,  Andrea Pierin ,  Stefano Gregori ,  Guido Torelli

IPC: H03M001/14

CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

Abstract: An analog-to-digital conversion method and device for a multilevel non-volatile memory devicethat includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different nullbit-layersnull, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.

Abstract translation: 用于多电平非易失性存储器设备的模数转换方法和装置包括多电平存储器单元。 该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。 在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。 还公开了一种用于多电平闪存中的错误控制编码的方案。 存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。 针对每个位层分别执行错误校正。 通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

公开(公告)号：US20020054505A1

公开(公告)日：2002-05-09

申请号：US09976473

申请日：2001-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C11/5642 ,  G11C8/00 ,  G11C11/56 ,  G11C11/5621

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract translation: 数据管理方法适用于具有由多个存储单元形成的存储器阵列的多级非易失性存储器件。 每个存储器单元存储不是2的整数倍的位数，例如3。 以这种方式，一个数据字节存储在非整数个存储单元中。 管理方法包括通过对预设数量的相邻存储器单元进行编程，以相同的时钟周期存储由多个字节形成的数据字。 通过在相同的时钟周期中读取存储的数据字来执行读取。

公开(公告)号：US20020041534A1

公开(公告)日：2002-04-11

申请号：US09919789

申请日：2001-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Gastaldi ,  Paolo Cappelletti ,  Giulio Casagrande ,  Giovanni Campardo ,  Rino Micheloni

IPC: G11C008/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.

Abstract translation: 诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。 属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列 形成包。 具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。 因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

公开(公告)号：US20040170057A1

公开(公告)日：2004-09-02

申请号：US10748696

申请日：2003-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Osama Khouri ,  Roberto Ravasio ,  Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C29/76

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract translation: 该设备包括用于扇区重新映射的电路，其具有与多路复用器单元相关联并且与多路复用器单元进行数据通信的CAM（内容可寻址存储器）单元。 CAM单元检测到扇区有故障，它提供替换扇区的预编程地址，并激活执行替换的多路复用器。 因此，有缺陷的扇区和地址图的相应位置有利地位于寻址区的后方。 因此，寻址区域是连续的，从而可以容易地存储和检索信息。

公开(公告)号：US20040145947A1

公开(公告)日：2004-07-29

申请号：US10706306

申请日：2003-11-12

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G11C016/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150), for programming a non-volatile memory device (100) having a plurality of memory cells (105), includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed. The driving elements are suitable to be supplied by a power supply unit (120,125), and a control means (145,150) controls the driving elements (115). The control means (145,150) includes means (150,205) for determining a residual capacity of the power supply unit, and a selecting means (145) selectively enables the driving elements (115) according to the residual capacity. A method of programming, an integrated circuit, and a computer system are also disclosed.

Abstract translation: 用于对具有多个存储单元（105）的非易失性存储器件（100）进行编程的电路（115,145,150）包括多个驱动元件（115），每个驱动元件用于向所选存储器单元施加编程脉冲， 程序。 驱动元件适于由电源单元（120,125）供电，并且控制装置（145,150）控制驱动元件（115）。 控制装置（145,150）包括用于确定电源单元的剩余容量的装置（150,205），以及选择装置（145）根据剩余容量有选择地启用驱动元件（115）。 还公开了编程方法，集成电路和计算机系统。

公开(公告)号：US20020099988A1

公开(公告)日：2002-07-25

申请号：US10003474

申请日：2001-10-25

Applicant: STMicroelectronics S.r.l.

Inventor： Khouri Osama ,  Stefano Gregori ,  Andrea Pierin ,  Rino Micheloni ,  Sergio Coronini ,  Guido Torelli

IPC: G11C029/00 ,  G06F007/02 ,  H03M013/00

CPC classification number: G11C27/005 ,  G11C7/062 ,  G11C11/5642 ,  G11C16/28 ,  G11C2207/063

Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

公开(公告)号：US20040223399A1

公开(公告)日：2004-11-11

申请号：US10675805

申请日：2003-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C008/02

CPC classification number: G11C29/82 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008 ,  G11C29/83 ,  G11C29/832

Abstract: The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.

Abstract translation: 本发明涉及一种用于精确定位擦除故障存储器单元的方法和可编程和电可擦除类型的相关集成非易失性存储器件，其包括以行和列布置的存储器单元的分区阵列，具有至少一个行 - 每个扇区的解码电路部分被提供正和负电压。 该方法在负擦除算法问题上变得可操作，并且包括以下步骤：强制尚未被完全擦除的扇区的读取条件; 扫描所述扇区的行以检查是否存在指示故障状态的杂散电流; 发现故障行并将其电隔离以将其重新寻址到在同一扇区中提供的冗余行。