公开(公告)号：US20190027566A1

公开(公告)日：2019-01-24

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/7881

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190027439A1

公开(公告)日：2019-01-24

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/535 ,  H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US20160308011A1

公开(公告)日：2016-10-20

申请号：US15195784

申请日：2016-06-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Julien DELALLEAU ,  Arnaud REGNIER

IPC: H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L29/788 ,  G11C16/14

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20200176577A1

公开(公告)日：2020-06-04

申请号：US16783401

申请日：2020-02-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11524

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190341462A1

公开(公告)日：2019-11-07

申请号：US16513145

申请日：2019-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  G11C16/04 ,  H01L29/78 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20190027447A1

公开(公告)日：2019-01-24

申请号：US16036639

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20150117109A1

公开(公告)日：2015-04-30

申请号：US14528780

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。

公开(公告)号：US20240347481A1

公开(公告)日：2024-10-17

申请号：US18753409

申请日：2024-06-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20230163083A1

公开(公告)日：2023-05-25

申请号：US18095136

申请日：2023-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/4916 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L23/528

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20180197963A1

公开(公告)日：2018-07-12

申请号：US15914846

申请日：2018-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11524 ,  H01L27/11521 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/28 ,  G11C16/14

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.