Abstract:
A non-volatile memory device includes a plurality of word lines stacked above a substrate in a vertical direction; erase control lines that are spaced apart from each other in a first direction and extend in a second direction; a pass transistor circuit including a first pass transistor connected to a first group of erase control lines and a second pass transistor connected to a second group of erase control lines; and a memory cell array including a plurality of blocks. The first group of erase control lines are relatively close to a word line cut region and the second group of erase control lines are relatively far from the word line cut region. Each of the plurality of blocks includes a plurality of channel structures connected to the word lines and the erase control lines and each channel structure extends in the vertical direction.
Abstract:
Disclosed is a server comprising: at least one processor; a communication circuit electrically connected to the at least one processor and transmitting or receiving a signal to/from an external device; and a memory electrically connected to the at least one processor and storing group information and control information, the group information representing at least one group including a group comprising a first electronic device and a second electronic device, and the control information being associated with each of the at least one group, wherein the at least one processor is configured so as to acquire demand response (DR)-associated information, and as a response to the DR-associated information, transmit the control information associated with the group to the first electronic device and the second electronic device. In addition, various embodiments are possible as identified in the specification.
Abstract:
A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.
Abstract:
A non-volatile memory device including a memory cell array including a plurality of cell strings, wherein each cell string of the plurality of cell stings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series between a bit line and a common source line; and a control circuit configured to perform a program operation on a selected memory cell from among the plurality of memory cells and pre-charge a selected cell string including the selected memory cell in a pre-charge section included in a verification section, wherein the selected cell string is pre-charged as a first pre-charge voltage is applied to a selected bit line connected to the selected memory cell.
Abstract:
An electronic device is provided. The electronic device includes an operation of determining at least one control level by executing at least one scheduling process, an operation of selecting one control level from among the at least one control level, and an operation of transmitting a power control signal corresponding to the selected control level to one or more control target devices. The operation of determining the control level may include an operation of performing a first scheduling process of receiving first power usage data from an external power amount data providing device and determining a first control level based on the first power usage data. In addition to this, various embodiments identified through the specification are possible.
Abstract:
An electronic device and a computer program product are provided herein. The electronic device includes: an audio module, a communication module, a microphone, a memory storing programming instructions, and a processor, which executes the program product, causing the electronic device to receive a voice command from a user via the microphone, request, upon receiving the voice command, situation information from a first external electronic device based on device information and the voice command, and after receiving the situation information, transmit the situation information to a second external electronic device via the communication module, and receiving content corresponding to the situation information from the second external electronic device and reproducing the received content
Abstract:
The present disclosure provides methods and apparatuses for reducing a program voltage rising time. In some embodiments, a flash memory includes a memory cell array including a plurality of memory cells, a target voltage generator configured to adjust a target voltage level of a word line recovery voltage provided to the plurality of memory cells, and a word line voltage controller configured to provide recovery control signals for controlling the target voltage level of the word line recovery voltage. The target voltage generator is further configured to adjust the word line recovery voltage provided to a selected word line to the target voltage level, based on the recovery control signals provided during a word line recovery operation following a program verify operation, and to reduce a program voltage rising time in a program execution operation period of a next program loop by adjusting the target voltage level.
Abstract:
A flash memory comprises a memory cell array having a plurality of memory cells; a read recovery voltage generator configured to provide a read recovery voltage to the plurality of memory cells; and a read recovery voltage controller configured to provide recovery control signals for controlling the read recovery voltage. The read recovery voltage generator includes a plurality of ground pass transistors that during a read recovery operation are configured to control a falling slope of an unselection recovery voltage provided to an unselected word line in response to the recovery control signals.
Abstract:
A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.
Abstract:
Disclosed are a method of recognizing a translation situation and performing a translation function, and an electronic device implementing the same. The electronic device recognizes a situation involving translation and automatically performs a translation function, thereby improving user convenience. An electronic device includes an audio module configured to receive and output audio signal, and a processor. A language translation program is executed in response to detecting that an audio signal received through the audio module includes at least a first language and a second language, a portion of the audio signal that is in the second language is translated into the first language, and the translated portion is outputted through the audio module.