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1.发明申请公开(公告)号：US20200343898A1
公开(公告)日：2020-10-29
申请号：US16516581
申请日：2019-07-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongrong ZUO , Chih-Wei Yao , Wanghua Wu
IPC: H03L7/099 , H03K17/687 , H01L29/78 , H04L7/033
Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.
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公开(公告)号：US10418981B2
公开(公告)日：2019-09-17
申请号：US15636387
申请日：2017-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing-Fai Loke , Chih-Wei Yao
Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.
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公开(公告)号：US09356555B2
公开(公告)日：2016-05-31
申请号：US14551970
申请日：2014-11-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai Loke , Chih-Wei Yao , Sunghwan Kim
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1243 , H03J2200/10
Abstract: Methods, apparatuses, and systems for providing a variable capacitance using an array of capacitor cells are discussed. In the fine tuning bank of an inductor/capacitor (LC)-tank of a digitally controlled oscillator (DCO), control is implemented by selecting a boundary cell from the array of capacitor cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.
Abstract translation: 讨论了使用电容器单元阵列提供可变电容的方法，装置和系统。 在数字控制振荡器（DCO）的电感器/电容器（LC）托盘的微调库中，通过从电容器单元阵列中选择边界单元并在电路中具有每个单元的边界单元之前实现控制 接地并且具有边界单元和电路中的边界单元之后的每个单元连接到电压源。 电路路径可以是在微调库中使用温度计编码形成的路径。
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公开(公告)号：US20160079919A1
公开(公告)日：2016-03-17
申请号：US14551970
申请日：2014-11-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing Fai LOKE , Chih-Wei Yao , Sunghwan Kim
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1212 , H03B5/1215 , H03B5/1225 , H03B5/1243 , H03J2200/10
Abstract: Methods, apparatuses, and systems for providing a variable capacitance using an array of capacitor cells are discussed. In the fine tuning bank of an inductor/capacitor (LC)-tank of a digitally controlled oscillator (DCO), control is implemented by selecting a boundary cell from the array of capacitor cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.
Abstract translation: 讨论了使用电容器单元阵列提供可变电容的方法，装置和系统。 在数字控制振荡器（DCO）的电感器/电容器（LC）托盘的微调库中，通过从电容器单元阵列中选择边界单元并在电路中具有每个单元的边界单元之前实现控制 接地并且具有边界单元和电路中的边界单元之后的每个单元连接到电压源。 电路路径可以是在微调库中使用温度计编码形成的路径。
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公开(公告)号：US11175633B2
公开(公告)日：2021-11-16
申请号：US16935827
申请日：2020-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chih-Wei Yao , Ronghua Ni
Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.
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Patent Agency Ranking
公开(公告)号：US10917078B2
公开(公告)日：2021-02-09
申请号：US16786364
申请日：2020-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wanghua Wu , Chih-Wei Yao
Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.
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公开(公告)号：US10581418B2
公开(公告)日：2020-03-03
申请号：US16019070
申请日：2018-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wanghua Wu , Chih-Wei Yao
Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.
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公开(公告)号：US20200014374A1
公开(公告)日：2020-01-09
申请号：US16572059
申请日：2019-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing-Fai Loke , Chih-Wei Yao
Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.
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公开(公告)号：US20180076821A1
公开(公告)日：2018-03-15
申请号：US15430163
申请日：2017-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wing-Fai LOKE , Chih-Wei Yao
CPC classification number: H03M1/1009 , G04F10/005 , G06F17/5081 , H03L7/0995 , H03L7/0996 , H03L7/0998 , H03M1/183
Abstract: An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.
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公开(公告)号：US11115005B2
公开(公告)日：2021-09-07
申请号：US16835778
申请日：2020-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Xiong Liu , Chih-Wei Yao
Abstract: A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage.
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