Semiconductor device
    1.
    发明授权

    公开(公告)号:US11705497B2

    公开(公告)日:2023-07-18

    申请号:US17185466

    申请日:2021-02-25

    CPC classification number: H01L29/42392 H01L29/0673 H01L29/512 H01L29/78696

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction intersecting the first direction on the active pattern, a gate spacer extending in the second direction along side walls of the gate electrode, an interlayer insulating layer contacting side walls of the gate spacer, a trench formed on the gate electrode in the interlayer insulating layer, a first capping pattern provided along side walls of the trench, at least one side wall of the first capping pattern having an inclined profile, and a second capping pattern provided on the first capping pattern in the trench.

    Semiconductor device
    3.
    发明授权

    公开(公告)号:US10998411B2

    公开(公告)日:2021-05-04

    申请号:US16406472

    申请日:2019-05-08

    Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

    Semiconductor device
    4.
    发明授权

    公开(公告)号:US10374085B2

    公开(公告)日:2019-08-06

    申请号:US15997793

    申请日:2018-06-05

    Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

    Semiconductor device
    5.
    发明授权

    公开(公告)号:US12224315B2

    公开(公告)日:2025-02-11

    申请号:US17516900

    申请日:2021-11-02

    Abstract: A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.

    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME

    公开(公告)号:US20240371876A1

    公开(公告)日:2024-11-07

    申请号:US18775521

    申请日:2024-07-17

    Abstract: A semiconductor device includes a substrate having a first power supply region, a second power supply region, and a cell region therein. The cell region extends between the first power supply region and the second power supply region. A first active region and a second active region are provided, which extend side-by-side within the cell region. A first power supply wiring is provided, which extends in the first direction within the first power supply region. A first source/drain contact is provided, which connects the first active region and the second active region. A second source/drain contact is provided, which connects the first active region and the first power supply wiring. The first source/drain contact includes a first recess portion disposed inside an intermediate region between the first active region and the second active region.

    Semiconductor device
    10.
    发明授权

    公开(公告)号:US12094976B2

    公开(公告)日:2024-09-17

    申请号:US17558967

    申请日:2021-12-22

    CPC classification number: H01L29/7851 H01L29/0847

    Abstract: A semiconductor device includes a first fin-shaped pattern which extends lengthwise in a first direction, a second fin-shaped pattern which is spaced apart from the first fin-shaped pattern in a second direction and extends lengthwise in the first direction, a first gate electrode extending lengthwise in the second direction on the first fin-shaped pattern, a second gate electrode extending lengthwise in the second direction on the second fin-shaped pattern, a first gate separation structure which separates the first gate electrode and the second gate electrode and is at the same vertical level as the first gate electrode and the second gate electrode, and a first source/drain contact extending lengthwise in the second direction on the first fin-shaped pattern and the second fin-shaped pattern. The first source/drain contact includes a first lower source/drain contact region which intersects the first fin-shaped pattern and the second fin-shaped pattern, and a first upper source/drain contact region which protrudes from the first lower source/drain contact region, and the first upper source/drain contact region does not overlap the first gate separation structure in the first direction.

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