公开(公告)号：US20240090211A1

公开(公告)日：2024-03-14

申请号：US18135349

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon KIM ,  Sung-Min HWANG ,  Dong-Sik LEE ,  Seunghyun CHO ,  Bongtae PARK ,  Jae-Joo SHIM

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.

公开(公告)号：US20240055486A1

公开(公告)日：2024-02-15

申请号：US18492445

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Young KIM ,  Dong-Sik LEE ,  Joon-Sung LIM ,  Bum Kyu KANG ,  Ho Jun SEONG

IPC: H01L29/10 ,  H10B43/27

CPC classification number: H01L29/1037 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

公开(公告)号：US20220336586A1

公开(公告)日：2022-10-20

申请号：US17504312

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Young KIM ,  Dong-Sik LEE ,  Joon-Sung LIM ,  Bum Kyu KANG ,  Ho Jun SEONG

IPC: H01L29/10 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate, a first stack structure on the substrate and includes a plurality of first gate electrodes, a second stack structure on the first stack structure and includes a plurality of second gate electrodes, a channel hole including a first lower channel hole that extends through a lower portion of the first stack structure, a first upper channel hole connected to the first lower channel hole, and a second channel hole connected to the first upper channel hole, and a channel structure in the channel hole. A side wall of the first lower channel hole has a first inclination relative to the first direction, a side wall of the first upper channel hole has a second inclination relative to the first direction, and a side wall of the second channel hole has a third inclination relative to the first direction.

公开(公告)号：US20210217760A1

公开(公告)日：2021-07-15

申请号：US17021416

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung YANG ,  Byungjin LEE ,  Bumkyu KANG ,  Dong-Sik LEE

IPC: H01L27/11539 ,  H01L27/11551 ,  H01L27/11543 ,  G11C16/08 ,  H01L27/11578 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US20230005942A1

公开(公告)日：2023-01-05

申请号：US17678473

申请日：2022-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Jae-Joo SHIM ,  Dong-Sik LEE ,  Bongtae PARK

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A 3D semiconductor memory device includes a substrate, a stack structure comprising interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, vertical channel structures penetrating the stack structure, a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer, an insulating layer covering the substrate and the stack structure, contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure, and a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor. A bottom surface of the first conductive contact is at a level lower than a bottom surface of the spacer.

公开(公告)号：US20190035808A1

公开(公告)日：2019-01-31

申请号：US16010743

申请日：2018-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Dong-Sik LEE ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522

Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.

公开(公告)号：US20170103999A1

公开(公告)日：2017-04-13

申请号：US15291521

申请日：2016-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Hoon LEE ,  Keejeong RHO ,  Sejun PARK ,  Jinhyun SHIN ,  Dong-Sik LEE ,  Woong-Seop LEE

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  G11C16/08 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157

Abstract: A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.