公开(公告)号：US12213315B2

公开(公告)日：2025-01-28

申请号：US17687131

申请日：2022-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjin Lee ,  Dong-Sik Lee ,  Joon-Sung Lim

IPC: H10B43/27 ,  H10B43/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/51

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

公开(公告)号：US08951881B2

公开(公告)日：2015-02-10

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US11626417B2

公开(公告)日：2023-04-11

申请号：US17113456

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Sik Lee ,  Byungjin Lee ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

公开(公告)号：US11587947B2

公开(公告)日：2023-02-21

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/1156 ,  H01L23/522 ,  H01L27/1158 ,  H01L23/528

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US20210320126A1

公开(公告)日：2021-10-14

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US10818678B2

公开(公告)日：2020-10-27

申请号：US15954151

申请日：2018-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Dong-Sik Lee ,  Joon-Sung Lim

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

公开(公告)号：US10700085B2

公开(公告)日：2020-06-30

申请号：US16010743

申请日：2018-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Dong-Sik Lee ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/1157 ,  H01L21/768 ,  H01L21/265 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/28

Abstract: A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.

公开(公告)号：US09711531B2

公开(公告)日：2017-07-18

申请号：US15285682

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Seop Lee ,  Jongyoon Choi ,  Jinhyun Shin ,  Dong-Sik Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L29/10 ,  H01L27/11568 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0243 ,  H01L21/02636 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/4234 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.

公开(公告)号：US11289504B2

公开(公告)日：2022-03-29

申请号：US16777776

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Dong-Sik Lee ,  Sung-Min Hwang ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/28 ,  H01L29/66

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US11069706B2

公开(公告)日：2021-07-20

申请号：US16573695

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11556

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.