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公开(公告)号：US09620193B2
公开(公告)日：2017-04-11
申请号：US14793749
申请日：2015-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doo-Hee Hwang , Sang-Kyu Kang , Dong-Yang Lee , Jae-Yeon Choi , Jong-Hyun Choi
IPC: G11C7/00 , G11C11/406 , G11C7/10
CPC classification number: G11C11/40611 , G11C7/1063 , G11C11/406
Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.
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2.发明授权Method of repairing a memory device and method of booting a system including the memory device 有权修复存储装置的方法和引导包括存储装置的系统的方法公开(公告)号：US09472305B2
公开(公告)日：2016-10-18
申请号：US14534492
申请日：2014-11-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Yeab Choo , Bu-Il Jung , Do-Geun Kim , Mi-Kyoung Park , Dong-Yang Lee , Sun-Young Lim , Ju-Yun Jung , Hyuk Han
CPC classification number: G11C29/04 , G11C29/78 , G11C29/785 , G11C29/88
Abstract: A method of repairing a memory device including a boot memory region, a normal memory region, and a redundant memory region, the redundant memory region including a plurality of repair memory units, includes repairing the boot memory region by performing at least one of excluding first fault memory units of the boot memory region from use as storage and replacing the first fault memory units with boot repair memory units of the repair memory units, each of the first fault memory units having at least one fault memory cell; and after the repairing the boot memory region, repairing the normal memory region by performing at least one of excluding second fault memory units from use as storage and replacing the second fault memory units with normal repair memory units of the repair memory units.
Abstract translation: 一种修复包括引导存储器区域，正常存储器区域和冗余存储器区域的存储器件的方法，所述冗余存储器区域包括多个修复存储器单元，包括通过执行以下操作中的至少一个修复引导存储器区域：排除第一 引导存储器区域的故障存储器单元用作存储，并且用修复存储器单元的引导修复存储器单元替换第一故障存储器单元，每个第一故障存储器单元具有至少一个故障存储器单元; 并且在修复引导存储器区域之后，通过执行排除第二故障存储器单元中的至少一个作为存储来修复正常存储器区域，并用修复存储器单元的正常修复存储器单元替换第二故障存储器单元。
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3.发明授权Nonvolatile memory device including a peripheral circuit to receive an address in synch with one of a rising and falling edge of a signal regardless of whether a first or second alignment type is selected and nonvolatile memory system including the same 有权非易失性存储器件包括外围电路，以接收与信号的上升沿和下降沿中的一个同步的地址，而不管是选择第一还是第二对准类型，并且包括其的非易失性存储器系统公开(公告)号：US09368168B2
公开(公告)日：2016-06-14
申请号：US14856218
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。
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公开(公告)号：US09715936B2
公开(公告)日：2017-07-25
申请号：US15062546
申请日：2016-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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公开(公告)号：US09281072B2
公开(公告)日：2016-03-08
申请号：US14856261
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
Abstract translation: 一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。
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Patent Agency Ranking
公开(公告)号：US20160005483A1
公开(公告)日：2016-01-07
申请号：US14856218
申请日：2015-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KYEONG-HAN LEE , Seok-Cheon Kwon , Dong-Yang Lee
CPC classification number: G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
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公开(公告)号：US09704571B2
公开(公告)日：2017-07-11
申请号：US15209126
申请日：2016-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Do-Kyun Kim , Dong-Yang Lee , Kwang-Hyun Kim
IPC: G11C11/24 , G11C11/56 , G11C11/4096 , G11C11/4094 , G11C11/4091
CPC classification number: G11C11/565 , G11C7/1006 , G11C11/4091 , G11C11/4094 , G11C11/4096
Abstract: A method of operating a memory device includes writing cell data having one of at least three states to a memory cell; amplifying a voltage level of a bit line connected to the memory cell; determining that the cell data is in a first state when the voltage level of the bit line sensed at a sensing point is equal to or greater than a first reference voltage; determining that the cell data is in a second state when the voltage level of the bit line sensed at the sensing point is equal to or less than a second reference voltage which has a lower voltage level than the first reference voltage; and determining that the cell data is in a third state when the cell data is not in the first or second states.
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公开(公告)号：US20150199230A1
公开(公告)日：2015-07-16
申请号：US14524476
申请日：2014-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MI-KYOUNG PARK , Dong-Yang Lee , Sun-Young Lim , Bu-Il Jung , Ju-Yun Jung , Sung-Ho Cho , Hee-Joo Choi , Min-Yeab Choo , Hyuk Han
IPC: G06F11/10
CPC classification number: G11C29/76 , G11C8/06 , G11C2029/4402
Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.
Abstract translation: 存储器系统包括存储器控制器，存储单元阵列，位置信息存储单元，地址映射表，地址转换单元和映射信息计算单元。 存储器控制器产生逻辑地址信号和地址重映射命令。 存储单元阵列包括多个逻辑块。 位置信息存储单元存储与包含在存储单元阵列中的故障存储单元对应的位置信息。 地址映射表存储地址映射信息。 地址转换单元基于地址映射信息将逻辑地址信号转换为对应于存储单元阵列的物理地址信号。 映射信息计算单元根据映射信息计算单元接收地址重映射命令，根据位置信息生成地址映射信息，以减少包括故障存储单元的逻辑块的数量。
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公开(公告)号：USRE49151E1
公开(公告)日：2022-07-26
申请号：US16381104
申请日：2019-04-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sun-Young Lim , Dong-Yang Lee , Young-Jin Cho , Oh-Seong Kwon
Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.
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公开(公告)号：US10083764B2
公开(公告)日：2018-09-25
申请号：US14524476
申请日：2014-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Mi-Kyoung Park , Dong-Yang Lee , Sun-Young Lim , Bu-Il Jung , Ju-Yun Jung , Sung-Ho Cho , Hee-Joo Choi , Min-Yeab Choo , Hyuk Han
CPC classification number: G11C29/76 , G11C8/06 , G11C2029/4402
Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.
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