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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY 审中-公开

    公开(公告)号：US20230360689A1

    公开(公告)日：2023-11-09

    申请号：US18307098

    申请日：2023-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Young Park ,  Joo Hwan Kim ,  Jin Do Byun ,  Eun Seok Shin ,  Hyun Sub Rie ,  Hyun-Yoon Cho ,  Jung Hwan Choi

    IPC: G11C11/4076 ,  H03K5/133 ,  H03L7/081 ,  H03K5/156

    CPC classification number: G11C11/4076 ,  H03K5/133 ,  H03L7/0812 ,  H03K5/1565 ,  H01L25/18

    Abstract: A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.

    Switched capacitor circuit to make amount of change in reference voltage even regardless of input level
    2.
    发明授权
    Switched capacitor circuit to make amount of change in reference voltage even regardless of input level 有权

    公开(公告)号：US10476449B2

    公开(公告)日：2019-11-12

    申请号：US15978233

    申请日：2018-05-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Woo Kim ,  Sun-Jae Park ,  Eun Seok Shin ,  Seunghoon Lee

    IPC: H03F3/45 ,  H03F3/00

    Abstract: A switched capacitor circuit includes a first main sampler circuit, a second main sampler circuit, a first replica sampler circuit, and a second replica sampler circuit. The first main sampler circuit samples a first input of a differential input, and generates a first output corresponding to the sampled first input based on a first reference voltage. The second main sampler circuit samples a second input of the differential input, and generates a second output corresponding to the sampled second input based on a second reference voltage. The first replica sampler circuit receives the first input, and holds the received first input based on the second reference voltage. The second replica sampler circuit receives the second input, and holds the received second input based on the first reference voltage.

    Memory device and method for calibrating the device and fabricating the device
    3.
    发明授权
    Memory device and method for calibrating the device and fabricating the device 有权

    公开(公告)号：US12112827B2

    公开(公告)日：2024-10-08

    申请号：US17852664

    申请日：2022-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joo Hwan Kim ,  Jun Young Park ,  Jin Do Byun ,  Kwang Seob Shin ,  Eun Seok Shin ,  Hyun-Yoon Cho ,  Young Don Choi ,  Jung Hwan Choi

    IPC: G11C7/10 ,  H03K19/00

    CPC classification number: G11C7/1048 ,  G11C2207/2254 ,  H03K19/0005

    Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

    Quantizer including capacitors and operating method of quantizer
    8.
    发明授权
    Quantizer including capacitors and operating method of quantizer 有权

    公开(公告)号：US10411726B2

    公开(公告)日：2019-09-10

    申请号：US16055193

    申请日：2018-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Woo Kim ,  Dai Shi ,  Eun Seok Shin

    IPC: H03M3/00 ,  H03M7/36

    Abstract: A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.

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