公开(公告)号：US09899497B2

公开(公告)日：2018-02-20

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Kyung Yub Jeon ,  Sujin Jung ,  Haegeon Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US09312181B2

公开(公告)日：2016-04-12

申请号：US14531987

申请日：2014-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Joon Choi ,  Myeongcheol Kim ,  Cheol Kim ,  GeumJung Seong ,  Hak-Sun Lee ,  Haegeon Jung ,  Ji-Eun Han

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。

公开(公告)号：US12068369B2

公开(公告)日：2024-08-20

申请号：US18348904

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon Park ,  Jongchul Park ,  Bokyoung Lee ,  Jeongyun Lee ,  Hyunggoo Lee ,  Yeondo Jung ,  Haegeon Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0657 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US20230352527A1

公开(公告)日：2023-11-02

申请号：US18348904

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Jongchul Park ,  Bokyoung Lee ,  Jeongyun Lee ,  Hyunggoo Lee ,  Yeondo Jung ,  Haegeon Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0657 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US11735627B2

公开(公告)日：2023-08-22

申请号：US17324610

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon Park ,  Jongchul Park ,  Bokyoung Lee ,  Jeongyun Lee ,  Hyunggoo Lee ,  Yeondo Jung ,  Haegeon Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0657 ,  H01L27/088 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US10593596B2

公开(公告)日：2020-03-17

申请号：US15959319

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09984931B2

公开(公告)日：2018-05-29

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.