公开(公告)号：US20170256709A1

公开(公告)日：2017-09-07

申请号：US15598605

申请日：2017-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchul PARK ,  Hyungjoon KWON ,  lnho KIM ,  Jongsoon PARK

IPC: H01L43/12 ,  H01L21/3213

CPC classification number: H01L43/12 ,  H01L21/32131 ,  H01L27/1087 ,  H01L27/222 ,  H01L43/08

Abstract: A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.

公开(公告)号：US20220102493A1

公开(公告)日：2022-03-31

申请号：US17324610

申请日：2021-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Jongchul PARK ,  Bokyoung LEE ,  Jeongyun LEE ,  Hyunggoo LEE ,  Yeondo JUNG ,  Haegeon JUNG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch.. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US20230352527A1

公开(公告)日：2023-11-02

申请号：US18348904

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Jongchul Park ,  Bokyoung Lee ,  Jeongyun Lee ,  Hyunggoo Lee ,  Yeondo Jung ,  Haegeon Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/0657 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

公开(公告)号：US20230307451A1

公开(公告)日：2023-09-28

申请号：US18326522

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inwon PARK ,  Bosoon KIM ,  Jongsoon PARK

IPC: H01L21/762 ,  H01L29/786 ,  H01L29/775 ,  H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

公开(公告)号：US20190189916A1

公开(公告)日：2019-06-20

申请号：US16284439

申请日：2019-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yil-hyung LEE ,  Jong-Kyu KIM ,  Jongchul PARK ,  Sang-Kuk KIM ,  Jongsoon PARK ,  Hyeji YOON ,  Woohyun LEE

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/222

Abstract: An ion beam apparatus may include a chamber assembly configured to hold a material and direct an ion beam on the material, a detector configured to detect a signal generated from the material based on the ion beam being directed on the material, and a controller configured to control at least one parameter associated with the chamber assembly based on the signal, such that at least one of an ion energy associated with the ion beam, an ion current associated with the ion beam, and an incident angle of the ion beam with respect to a top surface of the material is changed continuously with time.

公开(公告)号：US20250169187A1

公开(公告)日：2025-05-22

申请号：US18753484

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsoon PARK ,  Gunpil HWANG ,  Hyonwook RA ,  Keunhee BAI ,  Jinwook LEE ,  Sangho CHEON

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device may include a device isolation layer on a substrate and defining active regions extending a first direction; gate structures intersecting the active regions and extending in a second direction; channel layers spaced apart from each other on the active regions and surrounded by the gate structures; and source/drain regions connected to the channel layers and in recessed regions of the active regions on both sides of the gate structures. First and second regions of the substrate respectively may be spaced apart by a first length and the second length from first ends of the gate structures in the second direction. The second length may be longer than the first length. An upper surface of the device isolation layer may have recessed portion on the first region of the substrate and a flat upper surface on the second region of the substrate.

公开(公告)号：US20220199616A1

公开(公告)日：2022-06-23

申请号：US17394991

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inwon PARK ,  Bosoon KIM ,  Jongsoon PARK

IPC: H01L27/088 ,  H01L21/762 ,  H01L27/02

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

公开(公告)号：US20180182623A1

公开(公告)日：2018-06-28

申请号：US15661418

申请日：2017-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yil-hyung LEE ,  Jongchul PARK ,  Jong-Kyu KIM ,  Jongsoon PARK

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/263 ,  H01L21/31116

Abstract: A method of forming fine patterns includes forming an upper mask layer on a substrate, forming preliminary mask patterns on the upper mask layer, and forming upper mask patterns by etching the upper mask layer using the preliminary mask patterns as etch masks. Forming the upper mask patterns includes etching the upper mask layer by performing an etching process using an ion beam. The upper mask patterns include a first upper mask pattern formed under each of the preliminary mask patterns, and a second upper mask pattern formed between the preliminary mask patterns in a plan view and spaced apart from the first upper mask pattern.