公开(公告)号：US20140184312A1

公开(公告)日：2014-07-03

申请号：US14196602

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Eunseok CHO ,  Mi-Na CHOI ,  Kyoungsei CHOI ,  Heejung HWANG ,  Seran BAE

IPC: G05F1/46

CPC classification number: G05F1/463 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract translation: 示例性实施例涉及一种包括半导体封装的半导体器件，其中半导体芯片安装在封装衬底上。 半导体封装可以包括温度测量装置和温度控制电路。 温度测量装置可以测量半导体封装的温度。 温度控制电路可以基于由温度测量装置测量的半导体封装的温度来改变半导体封装的操作速度。

公开(公告)号：US20250062257A1

公开(公告)日：2025-02-20

申请号：US18435016

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Deuk KIM ,  Heejung HWANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor chip including a body that having a front surface and a rear surface; a wiring structure above the front surface of the body; a through via penetrating the body, and the through via is connected to the wiring structure; a heat dissipation structure above the rear surface of the body, and the heat dissipation structure includes a conductive layer connected to the through via; and a signal pad and a heat dissipation pad on the heat dissipation structure, and the signal pad and the heat dissipation pad are connected to the conductive layer.

公开(公告)号：US20240304564A1

公开(公告)日：2024-09-12

申请号：US18394974

申请日：2023-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbae KIM ,  Taehwan KIM ,  Heejung HWANG

IPC: H01L23/552 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/552 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265

Abstract: An electronic device includes a base substrate; a first package mounted on the base substrate, the first package including a first substrate and a first semiconductor chip mounted on the first substrate; a second package mounted on the first package, the second package including a second substrate, a second semiconductor chip mounted on the second substrate, a sealing material surrounding an upper surface of the second substrate and the second semiconductor chip, and a conformal conductive coating formed on at least an upper surface of the sealing material. A conductive fixing portion is secured to a ground pad exposed at an upper surface of the base substrate. A shielding can is secured to the base substrate by the conductive fixing portion and includes a side portion extending around the first and second packages. A metal paste is formed between the shielding can and the conformal conductive coating to contact the shielding can and the conformal conductive coating.

公开(公告)号：US20240079393A1

公开(公告)日：2024-03-07

申请号：US18218673

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Heejung HWANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A semiconductor package includes a package substrate including a substrate cavity, the substrate cavity extending from an upper surface of the package substrate toward a lower surface of the package substrate, a wiring interposer attached to the package substrate, a memory semiconductor structure attached to a lower surface of the wiring interposer, at least a portion of the memory semiconductor structure art being accommodated in the substrate cavity, a logic semiconductor chip attached to an upper surface of the wiring interposer, a conductive spacer spaced apart from the logic semiconductor chip in a horizontal direction, the conductive spacer being attached to the upper surface of the wiring interposer and overlapping the memory semiconductor structure in a vertical direction, and a heat dissipation member over the logic semiconductor chip and the conductive spacer.