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    DIGITAL-TO-ANALOG CONVERSION CIRCUIT AND RECEIVER INCLUDING THE SAME
    1.
    发明申请
    DIGITAL-TO-ANALOG CONVERSION CIRCUIT AND RECEIVER INCLUDING THE SAME 有权

    公开(公告)号：US20220149863A1

    公开(公告)日：2022-05-12

    申请号：US17306421

    申请日：2021-05-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

    IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03

    Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

    Phase interpolation based clock data recovery circuit and communication device including the same
    2.
    发明授权
    Phase interpolation based clock data recovery circuit and communication device including the same 有权

    公开(公告)号：US11456851B2

    公开(公告)日：2022-09-27

    申请号：US17469062

    申请日：2021-09-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanseok Kim ,  Hobin Song ,  Jaehyun Park

    IPC: H04L7/00 ,  H03L7/093 ,  H03L7/08 ,  H04L7/033

    Abstract: A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.

    Monotonic and glitch-free phase interpolator and communication device including the same
    5.
    发明授权
    Monotonic and glitch-free phase interpolator and communication device including the same 有权

    公开(公告)号：US11757437B2

    公开(公告)日：2023-09-12

    申请号：US17463617

    申请日：2021-09-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seuk Son ,  Hobin Song ,  Nakwon Lee

    IPC: H03K5/13 ,  H03K5/01 ,  H03K19/21 ,  G06F1/06 ,  H03M7/16 ,  H03K5/00

    CPC classification number: H03K5/01 ,  G06F1/06 ,  H03K19/21 ,  H03M7/165 ,  H03K2005/00058

    Abstract: A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.

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