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公开(公告)号：US10191805B2
公开(公告)日：2019-01-29
申请号：US15204536
申请日：2016-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Uhn Cha , Hoi-Ju Chung
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.
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公开(公告)号：US10090066B2
公开(公告)日：2018-10-02
申请号：US15696794
申请日：2017-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Uhn Cha , Hoi-Ju Chung , Jong-Pil Son , Kwang-Il Park , Seong-Jin Jang
Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.
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公开(公告)号：US11231996B2
公开(公告)日：2022-01-25
申请号：US17137535
申请日：2020-12-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Ho-Young Song , Hyun-Joong Kim
Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
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公开(公告)号：US10355833B2
公开(公告)日：2019-07-16
申请号：US16032544
申请日：2018-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Hyun-Joong Kim
Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
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5.发明申请公开(公告)号：US20180323915A1
公开(公告)日：2018-11-08
申请号：US16032544
申请日：2018-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoi-Ju Chung , Sang-Uhn Cha , Hyun-Joong Kim
CPC classification number: H04L1/24 , G06F11/1048 , G11C29/52 , G11C2029/0411
Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
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Patent Agency Ranking
公开(公告)号：US09990163B2
公开(公告)日：2018-06-05
申请号：US15290339
申请日：2016-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Uhn Cha , Hoi-Ju Chung , Uk-Song Kang
CPC classification number: G06F3/0679 , G06F3/0619 , G06F3/064 , G06F11/106 , G11C11/1673 , G11C11/1675 , G11C29/52
Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.
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7.发明授权Nonvolatile memory device using a resistance material and a driving method thereof 有权使用电阻材料的非易失性存储器件及其驱动方法公开(公告)号：US09299429B2
公开(公告)日：2016-03-29
申请号：US14317162
申请日：2014-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Jun Lee , Hoi-Ju Chung , Yong-Jin Kwon , Hyo-Jin Kwon , Eun-Hye Park
CPC classification number: G11C13/004 , G11C7/1039 , G11C7/1042 , G11C11/5678 , G11C11/5685 , G11C13/0061 , G11C2213/71 , G11C2213/72
Abstract: A nonvolatile memory device includes a buffer memory, a read circuit configured to read first data stored in the buffer memory in a first read operation, and a write circuit configured to write second data in the buffer memory in a first write operation, wherein the first write operation is performed when a first internal write command is generated during the first read operation.
Abstract translation: 非易失性存储器件包括缓冲存储器，被配置为在第一读取操作中读取存储在缓冲存储器中的第一数据的读取电路和被配置为在第一写入操作中将第二数据写入缓冲存储器的写入电路，其中第一 在第一读取操作期间产生第一内部写入命令时执行写入操作。
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8.发明授权公开(公告)号：US09093146B2
公开(公告)日：2015-07-28
申请号：US14171849
申请日：2014-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Hye Park , Hoi-Ju Chung , Yong-Jin Kwon , Hyo-Jin Kwon , Yong-Jun Lee
CPC classification number: G11C13/0061 , G11C13/0002 , G11C13/004 , G11C2213/72
Abstract: A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.
Abstract translation: 非易失性存储器件包括存储器芯，其包括多个可变电阻存储器单元，输入/输出（I / O）电路被配置为依次接收第一分组信号和第二分组信号，第一和第二分组信号共同地包括 用于存储器访问操作的信息，并且还被配置为在解码所述第一分组信号时发起核心访问操作，并且在解码所述第二分组信号时选择性地继续或中断所述核心访问操作;以及读取电路，被配置为执行所述核心的一部分 在第二分组信号被解码之前响应于第一分组信号的接入操作。
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9.发明授权公开(公告)号：US10255989B2
公开(公告)日：2019-04-09
申请号：US15233088
申请日：2016-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Uhn Cha , Hoi-Ju Chung
IPC: G06F11/10 , G11C29/52 , G11C11/406 , G11C11/4096 , G11C11/408 , G11C11/4076 , G11C29/00 , G11C11/16
Abstract: A semiconductor memory device includes a memory cell array and a main controller. The memory cell array includes a plurality of memory bank arrays, and each of the memory bank arrays includes a plurality of pages. The main controller counts a number of accesses to a first memory region of the memory cell array, generates at least one victim address of at least one neighbor memory region that is adjacent to the first memory region and performs a scrubbing operation sub-pages of the pages corresponding to the at least one victim address when the counted number of accesses reaches a first reference value during a reference interval.
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公开(公告)号：US10198221B2
公开(公告)日：2019-02-05
申请号：US15969042
申请日：2018-05-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Uhn Cha , Hoi-Ju Chung , Uk-Song Kang
Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.
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