公开(公告)号：US11729974B2

公开(公告)日：2023-08-15

申请号：US17182479

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Jaeho Hong

IPC: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.

公开(公告)号：US11581316B2

公开(公告)日：2023-02-14

申请号：US17092593

申请日：2020-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/102 ,  H01L29/74

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

公开(公告)号：US11350377B2

公开(公告)日：2022-05-31

申请号：US16625627

申请日：2018-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeuk Lee ,  Hyuncheol Kim

IPC: H04W56/00 ,  H04W74/08

Abstract: The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data rate, after a 4G communication system such as an LTE system. The present invention relates to a method for guaranteeing a quality of a service in a wireless communication system. Specifically, a method for a base station according to an embodiment of the present invention comprises the steps of: receiving a PRACH from a terminal; identifying a transmission pattern of the PRACH for a symbol group including a plurality of symbols transmitted in a single tone; acquiring information of phase difference between tones, in which the PRACH has been received, according to multiple intervals between symbol groups on the basis of the transmission pattern of the PRACH; estimating a phase offset on the basis of the information of phase difference; and generating uplink timing information for transmission to the terminal, by using a timing offset converted from the estimated phase offset.

公开(公告)号：US10148315B2

公开(公告)日：2018-12-04

申请号：US15552990

申请日：2016-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesang Ham ,  Hyuncheol Kim ,  Yusuk Yun

IPC: H04B1/71 ,  H04B1/7117 ,  H04B1/709 ,  H04B7/08

Abstract: The present invention relates to a method and a device for adjusting a signal of a receiving device in a mobile communication system and, more specifically, to a method for adjusting a signal of a receiving device in a mobile communication system, the method comprising the steps of: receiving signals from at least two antennas; calculating at least one correlation value by using the received signals; obtaining a delay difference value between the signals based on the at least one calculated correlation value; and outputting adjusted signals generated by adjusting the received signals based on the obtained delay difference value.

公开(公告)号：US12279435B2

公开(公告)日：2025-04-15

申请号：US17683460

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

公开(公告)号：US12034026B2

公开(公告)日：2024-07-09

申请号：US17465217

申请日：2021-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Kyungho Lee ,  Kazunori Kakehi ,  Doosik Seol ,  Kyungduck Lee ,  Taesub Jung ,  Masato Fujita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14683

Abstract: An image sensor includes a substrate having first and second surfaces, pixel regions arranged in a direction parallel to the first surface, first and second photodiodes isolated from each other in each of the pixel regions, a first device isolation film between the pixel regions, a pair of second device isolation films between the first and second photodiodes and extending from the first device isolation film, a doped layer adjacent to the pair of second device isolation films and extending from the second surface to a predetermined depth and spaced apart from the first surface, the doped layer being isolated from the first device isolation film, and a barrier area between the pair of second device isolation films and having a potential greater than a potential of a portion of the substrate adjacent to the barrier area.

公开(公告)号：US11862220B2

公开(公告)日：2024-01-02

申请号：US17836228

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C11/22 ,  G11C5/06

CPC classification number: G11C11/2273 ,  G11C5/06 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2275

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

公开(公告)号：US11621264B2

公开(公告)日：2023-04-04

申请号：US16999378

申请日：2020-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L27/102 ,  H01L29/24 ,  H01L29/66 ,  H01L29/87 ,  H01L29/74 ,  H01L27/108 ,  H01L27/06

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

公开(公告)号：US20220108741A1

公开(公告)日：2022-04-07

申请号：US17362138

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEHO HONG ,  Hyuncheol Kim ,  Yongseok Kim ,  Iigweon Kim ,  Hyeongwon Seo ,  Sungwon Yoo ,  Kyunghwan Lee

IPC: G11C11/402 ,  H01L27/102 ,  H01L29/66 ,  H01L29/749

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

公开(公告)号：US20220028859A1

公开(公告)日：2022-01-27

申请号：US17191308

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho HONG ,  Kyunghwan Lee ,  Hyuncheol Kim ,  Huijung Kim ,  Hyunmog Park ,  Kiseok Lee ,  Minhee Cho

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/24

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.