公开(公告)号：US20190164989A1

公开(公告)日：2019-05-30

申请号：US16122037

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun LEE ,  Jae-Hoon JANG ,  Jae-Duk LEE ,  Joon-Hee LEE ,  Young-Jin JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/308 ,  H01L21/76837 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/40117

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US20130242667A1

公开(公告)日：2013-09-19

申请号：US13867716

申请日：2013-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/14 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20230268017A1

公开(公告)日：2023-08-24

申请号：US18310843

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/04 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  H10B43/27 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/3418 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  H10B43/27 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  H10B43/35

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20200381453A1

公开(公告)日：2020-12-03

申请号：US16995084

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun LEE ,  Jae-Hoon JANG ,  Jae-Duk LEE ,  Joon-Hee LEE ,  Young-Jin JUNG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L27/11556 ,  H01L21/28

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US20220093195A1

公开(公告)日：2022-03-24

申请号：US17542183

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20190096495A1

公开(公告)日：2019-03-28

申请号：US16206383

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20200234782A1

公开(公告)日：2020-07-23

申请号：US16844317

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20150117118A1

公开(公告)日：2015-04-30

申请号：US14590665

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/14

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20140048873A1

公开(公告)日：2014-02-20

申请号：US14057094

申请日：2013-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joo SHIM ,  Han-Soo KIM ,  Won-Seok CHO ,  Jae-Hoon JANG ,  Sang-Yong PARK

IPC: H01L29/78

CPC classification number: H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

Abstract: A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

Abstract translation: 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。