公开(公告)号：US20250070765A1

公开(公告)日：2025-02-27

申请号：US18813909

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/3562 ,  H03K3/012

Abstract: A flip-flop is provided. The flip-flop includes: a master latch; and a slave latch. The master latch includes: a first circuit configured to, based on a clock signal, a data input signal, and a first data signal, generate a second data signal complementary to the data input signal; a second circuit configured to, based on the clock signal, an inverted data input signal, and the second data signal, generate the first data signal complementary to the inverted data input signal; and a third circuit configured to generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal. The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

公开(公告)号：US20250080119A1

公开(公告)日：2025-03-06

申请号：US18818024

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K23/56 ,  H03K23/44 ,  H03M1/48

Abstract: Disclosed are a bidirectional counter and a method of generating output data. The bidirectional counter may include at least one first flip-flop configured to generate, based on at least one first local clock, at least one first bit including a least significant bit (LSB) of the output data and a second bit that is an upper bit of the at least one first bit, and a local clock generation circuit configured to generate, in response to an up signal that is activated, the at least one first local clock based on the input clock and the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit.

公开(公告)号：US10749527B2

公开(公告)日：2020-08-18

申请号：US16056072

申请日：2018-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dalhee Lee ,  Jintae Kim ,  Jaeha Lee

IPC: H03K19/0175 ,  H03K19/0185

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

公开(公告)号：US09690896B2

公开(公告)日：2017-06-27

申请号：US15094280

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Seo ,  Jaeha Lee

IPC: H01L21/00 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/76816 ,  H01L21/76892 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

Abstract: A method for manufacturing a semiconductor device is provided. The method includes disposing pre-conductive lines and post-conductive lines for forming first and second cells. The first and second cells are adjacent to each other in a first direction. A first conductive line of the first cell extends in a second direction perpendicular to the first direction and is adjacent to a boundary between the first and second cells. A second conductive line and a third conductive line of the second cell extend in the first direction and are adjacent to the boundary. The second and third conductive lines are respectively disposed on two non-adjacent tracks, among a plurality of tracks that extend in the first direction. The first conductive line intersects one of the two non-adjacent tracks and one track disposed between the two non-adjacent tracks.

公开(公告)号：US20250070764A1

公开(公告)日：2025-02-27

申请号：US18812235

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-sun Kong ,  Bomin Joo

IPC: H03K3/356 ,  G11C7/06

Abstract: A sense amplifier flip-flop includes a first stage configured to generate, in response to a rising edge of a clock signal, a first latch signal and a second latch signal by pulling down a first pull-down node or a second pull-down node according to a data input and an inverted data input, wherein the first stage includes a bridge circuit configured to electrically connect the first pull-down node and the second pull-down node to each other in response to an activated bridge signal, and a control circuit configured to activate the bridge signal when the data input transitions while the clock signal is logic high.

公开(公告)号：US20250070763A1

公开(公告)日：2025-02-27

申请号：US18812395

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/037

Abstract: A flip-flop configured to generate an output toggling according to an input clock includes an inverter configured to generate the output by inverting a first data signal, a first circuit configured to generate a second data signal based on an input clock and a latch signal, a second circuit configured to generate the latch signal based on the input clock and the second data signal, and a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal, wherein the third circuit is further configured to pull down the first data signal, independently of the second data signal, using the input clock and the latch signal.

公开(公告)号：US11635821B2

公开(公告)日：2023-04-25

申请号：US17081597

申请日：2020-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonah Park ,  Jaeyong Ju ,  Taehyeong Kim ,  Jaeha Lee

IPC: G06F3/01 ,  G06V40/20 ,  G06F3/00 ,  G06F3/03 ,  G06V40/19

Abstract: An electronic apparatus is provided. The electronic apparatus includes a camera; a memory configured to store at least one instruction; and at least one processor configured to execute the at least one instruction to: detect at least one object included in an image captured by the camera; identify information on an engagement of each of the at least one object with the electronic apparatus; obtain gesture information of each of the at least one object; obtain a target object from among the at least one object based on an operation status of the electronic apparatus, the information on the engagement of each of the at least one object, and the obtained gesture information of each of the at least one object; identify a function corresponding to gesture information of the target object; and execute the identified function.

公开(公告)号：US11387229B2

公开(公告)日：2022-07-12

申请号：US16826756

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha Lee ,  Ha-Young Kim ,  Bonghyun Lee ,  Soyoung Lee ,  Yongeun Cho

IPC: H01L29/76 ,  H01L27/02 ,  G06F30/398 ,  G06F30/394 ,  G06F30/392

Abstract: Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

公开(公告)号：US20220189945A1

公开(公告)日：2022-06-16

申请号：US17545009

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha Lee ,  Jintae Kim ,  Keunho Lee ,  Dongyeon Heo

IPC: H01L27/02 ,  G06F30/392

Abstract: An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line.

公开(公告)号：US20210343699A1

公开(公告)日：2021-11-04

申请号：US17147567

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Jaeha Lee ,  Dongyeon Heo

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/394

Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length.