公开(公告)号：US20170110177A1

公开(公告)日：2017-04-20

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho LEE ,  Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40615 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/40618

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

公开(公告)号：US20150037937A1

公开(公告)日：2015-02-05

申请号：US14486372

申请日：2014-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Min PARK ,  Jong-Ho LEE

IPC: H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4817 ,  H01L21/50 ,  H01L23/552 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Abstract translation: 提供了包括EMI屏蔽的半导体器件，其制造方法，包括该半导体器件的半导体模块以及包括该半导体器件的电子系统。 半导体器件包括下半导体封装，上半导体封装，封装凸块和EMI屏蔽。 下半导体封装包括下基板，安装在下基板上的下半导体芯片以及与下半导体芯片分离的接地线。 上半导体封装包括堆叠在下半导体封装上的上基板和堆叠在上基板上的上半导体芯片。 封装凸块电连接上半导体封装和下半导体封装。 EMI屏蔽覆盖上半导体封装和下半导体封装，并且电连接到地线。

公开(公告)号：US20150357298A1

公开(公告)日：2015-12-10

申请号：US14637545

申请日：2015-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Gwon JANG ,  Jong-Ho LEE ,  Ae-Nee JANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/2511 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1441 ,  H01L2224/03

Abstract: A semiconductor chip includes a semiconductor chip die having a first surface and a second surface facing the first surface, a connection pad on the first surface of the semiconductor chip die, and a redistribution pad arranged on the first surface of the semiconductor chip die and electrically connected to the connection pad and including an end portion having a concave-convex structure and extended to a lateral surface of the semiconductor chip die.

Abstract translation: 半导体芯片包括具有第一表面和面向第一表面的第二表面的半导体芯片裸片，半导体芯片裸片的第一表面上的连接焊盘和布置在半导体芯片裸片的第一表面上的再分布焊盘， 连接到连接焊盘并且包括具有凹凸结构并延伸到半导体芯片裸片的侧表面的端部。

公开(公告)号：US20150004783A1

公开(公告)日：2015-01-01

申请号：US14286170

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho LEE ,  Min-Keun KWAK ,  Bum-Joon YOUN ,  Sung-Won CHOI

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823842 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545

Abstract: A method for making a semiconductor device includes forming a trench in a first layer on a substrate. A conductive layer having a pattern is formed in the trench. A first metal gate electrode is formed on the conductive layer, and a second metal gate electrode is formed on the first metal gate electrode. The first and second metal gate electrodes at least partially conform to the pattern of the conductive layer. Widths of first surfaces of the first and second metal gate electrodes are different from respective widths of second surfaces of the first and second metal gate electrodes as a result of the pattern.

Abstract translation: 制造半导体器件的方法包括在衬底上的第一层中形成沟槽。 在沟槽中形成具有图案的导电层。 第一金属栅电极形成在导电层上，第二金属栅电极形成在第一金属栅电极上。 第一和第二金属栅电极至少部分地符合导电层的图案。 作为图案的结果，第一和第二金属栅电极的第一表面的宽度不同于第一和第二金属栅电极的第二表面的宽度。

公开(公告)号：US20130256847A1

公开(公告)日：2013-10-03

申请号：US13778467

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-Min PARK ,  Jong-Ho LEE

IPC: H01L23/58 ,  H01L21/50

CPC classification number: H01L21/4817 ,  H01L21/50 ,  H01L23/552 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

公开(公告)号：US20140167177A1

公开(公告)日：2014-06-19

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jong-Mil YOUN ,  Jong-Ho LEE

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。