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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11587897B2

    公开(公告)日：2023-02-21

    申请号：US17143224

    申请日：2021-01-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongwon Shin ,  Yeonjin Lee ,  Inyoung Lee ,  Jimin Choi ,  Jung-Hoon Han

    IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00

    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a conductive pad on a first surface of the semiconductor substrate, a passivation layer on the first surface of the semiconductor substrate, the passivation layer having a first opening that exposes the conductive pad, an organic dielectric layer on the passivation layer, the organic dielectric layer having a second opening, and a bump structure on the conductive pad and in the first and second openings. The organic dielectric layer includes a material different from a material of the passivation layer. The second opening is spatially connected to the first opening and exposes a portion of the passivation layer. The bump structure includes a pillar pattern in contact with the passivation layer and the organic dielectric layer.

    Semiconductor devices including a thick metal layer
    2.
    发明授权
    Semiconductor devices including a thick metal layer 有权

    公开(公告)号：US11616018B2

    公开(公告)日：2023-03-28

    申请号：US17398043

    申请日：2021-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

    IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

    Semiconductor devices including a thick metal layer
    3.
    发明授权
    Semiconductor devices including a thick metal layer 有权

    公开(公告)号：US11133253B2

    公开(公告)日：2021-09-28

    申请号：US16885438

    申请日：2020-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juik Lee ,  Joongwon Shin ,  Jihoon Chang ,  Junghoon Han ,  Junwoo Lee

    IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME 有权

    公开(公告)号：US20250079296A1

    公开(公告)日：2025-03-06

    申请号：US18624828

    申请日：2024-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjun Song ,  Jongmin Lee ,  Joongwon Shin

    IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor device includes an interconnection region including lower interconnections on a device region; an insulating structure on the interconnection region; lower conductive patterns in the insulating structure; a first conductive via electrically connecting the lower conductive patterns to the lower interconnections; upper conductive patterns on the insulating structure; and second conductive vias in the insulating structure and electrically connecting the upper conductive patterns to the lower conductive patterns. The second conductive vias include a second metal layer and a second barrier layer, and the upper conductive patterns include a third barrier layer extending from the second barrier layer and on a portion of an upper surface of the insulating structure; a third metal layer on the third barrier layer and extending from the second metal layer; an upper metal layer on the third metal layer; and an upper anti-reflective layer on the upper metal layer.

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