公开(公告)号：US20170207130A1

公开(公告)日：2017-07-20

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung PARK ,  Ju-Hyun KIM ,  Hoyoung KIM ,  Boun YOON ,  TaeYong KWON ,  Sangkyun KIM ,  Sanghyun PARK

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L21/3105

CPC classification number: H01L21/823807 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US20190148632A1

公开(公告)日：2019-05-16

申请号：US16122056

申请日：2018-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Min LEE ,  Ju-Hyun KIM ,  Jung-Hwan PARK ,  Se-Chung OH ,  Dong-Kyu LEE ,  Kyung-Il HONG

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22

Abstract: In a method of manufacturing a variable resistance memory device, an MTJ structure layer is formed on a substrate. The MTJ structure layer is etched in an etching chamber to form an MTJ structure. The substrate having the MTJ structure thereon is transferred to a deposition chamber through a transfer chamber. A protection layer covering a sidewall of the MTJ structure is formed in the deposition chamber. The etching chamber, the transfer chamber, and the deposition chamber are kept in a high vacuum state equal to or more than about 10−8 Torr.

公开(公告)号：US20190385918A1

公开(公告)日：2019-12-19

申请号：US16245686

申请日：2019-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Young CHOI ,  Zhan ZHAN ,  Min-Seob KIM ,  Ju-Hyun KIM ,  Sung-Gun KANG ,  Hwa-Sung RHEE

IPC: H01L21/66 ,  G01R31/26

Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.

公开(公告)号：US20190097124A1

公开(公告)日：2019-03-28

申请号：US16101243

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-Myoung LEE ,  Ju-Hyun KIM ,  Jung-Hwan PARK ,  Se-Chung OH ,  Young-Man JANG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM device includes a lower electrode, a blocking pattern on the lower electrode and including a binary metal boride in an amorphous state, a seed pattern on the blocking pattern and including a metal, an MTJ structure on the seed pattern, and an upper electrode on the MTJ structure.