公开(公告)号：US20220293426A1

公开(公告)日：2022-09-15

申请号：US17553049

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Lee ,  Duck-Nam Kim ,  Keunhee Bai ,  Sae IL Son ,  Kwang-Ho You ,  Cheolin Jang

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.

公开(公告)号：US11769811B2

公开(公告)日：2023-09-26

申请号：US17548826

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongho Jeon ,  Sekoo Kang ,  Keunhee Bai ,  Dongseok Lee

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364

Abstract: A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction.

公开(公告)号：US11201224B2

公开(公告)日：2021-12-14

申请号：US16820302

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongho Jeon ,  Sekoo Kang ,  Keunhee Bai ,  Dongseok Lee

IPC: H01L29/423 ,  H01L29/40

Abstract: A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction.

公开(公告)号：US20250142952A1

公开(公告)日：2025-05-01

申请号：US18796895

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Dongkwon Kim ,  Myeongji Kim ,  Sangduk Park ,  Keunhee Bai ,  Gahyun Lim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L25/18 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of manufacturing an integrated circuit device is provided. The method includes: providing a substrate including a base substrate layer, an insulating substrate layer, and a cover substrate layer that are sequentially stacked in a vertical direction; forming, on the substrate, a stacked structure including a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers that are alternately stacked one layer at a time; and forming a plurality of trench regions to define a plurality of fin-type active regions by etching the stacked structure and the substrate. The he forming of the plurality of trench regions includes, by using the insulating substrate layer as an etch stop layer, etching portions of the stacked structure and the cover substrate layer in the vertical direction up to an upper surface of the insulating substrate layer.

公开(公告)号：US11031392B2

公开(公告)日：2021-06-08

申请号：US16703908

申请日：2019-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongho Jeon ,  Sekoo Kang ,  Sungwoo Myung ,  Keunhee Bai

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12

Abstract: An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.

公开(公告)号：US20200348599A1

公开(公告)日：2020-11-05

申请号：US16676588

申请日：2019-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunhee Bai ,  Jinhong Park ,  Jinseok Heo ,  Seungmin Lee ,  Suntaek Lim

IPC: G03F7/20 ,  H01L21/268

Abstract: Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.

公开(公告)号：US20200312844A1

公开(公告)日：2020-10-01

申请号：US16703908

申请日：2019-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongho Jeon ,  Sekoo Kang ,  Sungwoo Myung ,  Keunhee Bai

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49

Abstract: An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.

公开(公告)号：US12100596B2

公开(公告)日：2024-09-24

申请号：US17553049

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Lee ,  Duck-Nam Kim ,  Keunhee Bai ,  Sae Il Son ,  Kwang-Ho You ,  Cheolin Jang

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76811

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.

公开(公告)号：US20230395674A1

公开(公告)日：2023-12-07

申请号：US18236823

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongho Jeon ,  Sekoo Kang ,  Keunhee Bai ,  Dongseok Lee

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L29/42364 ,  H01L29/401

Abstract: A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction.

公开(公告)号：US11086224B2

公开(公告)日：2021-08-10

申请号：US16676588

申请日：2019-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunhee Bai ,  Jinhong Park ,  Jinseok Heo ,  Seungmin Lee ,  Suntaek Lim

IPC: G03F7/20 ,  H01L21/268

Abstract: Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.