公开(公告)号：US20230352410A1

公开(公告)日：2023-11-02

申请号：US18347512

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Kwangjin Moon ,  Hojin Lee ,  Pilkyu Kang ,  Hoonjoo Na

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having a first and second surface opposite to each other, and an active region on the first surface and defined by a first isolation region; a plurality of active fins on the active region, extending in a first direction, and defined by a second isolation region having a second depth smaller than a first depth of the first isolation region; a buried conductive wiring in a trench adjacent to the fins, and extending in a direction of the trench; a filling insulation portion in the trench, and having the wiring therein; an interlayer insulation layer on the first and second isolation regions and on the buried conductive wiring; a contact structure penetrating the interlayer insulation layer, and contacting the buried conductive wiring; and a conductive through structure extending through the substrate from the second surface to the trench, and contacting the buried conductive wiring.

公开(公告)号：US11600553B2

公开(公告)日：2023-03-07

申请号：US17381287

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungjoo Park ,  Jaewon Hwang ,  Kwangjin Moon ,  Kunsang Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

公开(公告)号：US11581279B2

公开(公告)日：2023-02-14

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US20220013503A1

公开(公告)日：2022-01-13

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US20210375722A1

公开(公告)日：2021-12-02

申请号：US17147927

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam Kim ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

公开(公告)号：US11101196B2

公开(公告)日：2021-08-24

申请号：US16795686

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungjoo Park ,  Jaewon Hwang ,  Kwangjin Moon ,  Kunsang Park

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

公开(公告)号：US20210066250A1

公开(公告)日：2021-03-04

申请号：US16855352

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuha Lee ,  Pilkyu Kang ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Jaehyung Park ,  Joohee Jang ,  Yikoan Hong

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.

公开(公告)号：US10103098B2

公开(公告)日：2018-10-16

申请号：US15403480

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung Jung ,  Kwangjin Moon ,  Byung Lyul Park ,  Jin Ho An

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

公开(公告)号：US11908775B2

公开(公告)日：2024-02-20

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US11824035B2

公开(公告)日：2023-11-21

申请号：US17826756

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyung Park ,  Seokho Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Kyuha Lee ,  Joohee Jang

IPC: H01L23/00 ,  H10K19/20 ,  H10K39/32 ,  H01L27/146

CPC classification number: H01L24/32 ,  H01L24/83 ,  H10K19/20 ,  H10K39/32 ,  H01L27/14647 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/83359 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-κ dielectric material.