公开(公告)号：US20240133683A1

公开(公告)日：2024-04-25

申请号：US18460929

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho KWAK ,  Jinsun KIM ,  Moosong LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG ,  Dohyeon PARK ,  Yeeun HAN

IPC: G01B15/00

CPC classification number: G01B15/00

Abstract: In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.

公开(公告)号：US20220128897A1

公开(公告)日：2022-04-28

申请号：US17358785

申请日：2021-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moosong LEE ,  Seongbo SHIM

IPC: G03F1/22

Abstract: An EUV photomask may include a multi-layered structure on a substrate, a capping layer on the multi-layered structure, and an absorber on the capping layer. The absorber may include a first sidewall and a second sidewall. The first sidewall may extend from an upper surface of the capping layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and may be a flat plane. The second sidewall may extend from the first sidewall in the vertical direction, and may be a curved surface.

公开(公告)号：US20240071751A1

公开(公告)日：2024-02-29

申请号：US18237712

申请日：2023-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moosong LEE ,  Sangho YUN ,  Hyoungkook Kim

IPC: H01L21/02 ,  H01L21/449 ,  H01L21/67

CPC classification number: H01L21/02282 ,  H01L21/449 ,  H01L21/6715 ,  H01L21/67253 ,  G03F7/162

Abstract: A method of manufacturing a semiconductor device. The method includes providing a viscous solution to a wafer, spinning the wafer to coat at least a portion of the wafer with the viscous solution, and treating the wafer coated with the viscous solution, by using an acoustic wave, wherein a frequency of the acoustic wave and an eigenfrequency of the wafer coated with the viscous solution are same.

公开(公告)号：US20240045336A1

公开(公告)日：2024-02-08

申请号：US18133118

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sookyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: G03F7/20 ,  G03F7/004

CPC classification number: G03F7/2004 ,  G03F7/2022 ,  G03F7/0045

Abstract: A method for forming a resist pattern is disclosed. According to the method, a photosensitive layer is formed on a substrate by using an inorganic photoresist. The photosensitive layer is irradiated with a deep ultraviolet (DUV) light. The photosensitive layer is irradiated with an extreme ultraviolet (EUV) light after the irradiation of the DUV light. The photosensitive layer exposed to the EUV light is heated. The heated photosensitive layer is developed.

公开(公告)号：US20230411393A1

公开(公告)日：2023-12-21

申请号：US18140789

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moosong LEE ,  Jinsun KIM ,  Inho KWAK ,  Dohyeon PARK ,  Yeeun HAN ,  Sang-Ho YUN ,  Seungyoon LEE ,  Nanhyung KIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L27/0207 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a key region, a dummy active pattern on the key region, the dummy active pattern including a first impurity region and a second impurity region, a line structure provided on the first impurity region and extended in a first direction, a dummy gate electrode provided between the first and second impurity regions and extended in a second direction crossing the first direction, and a dummy contact disposed adjacent to a side of the line structure and connected to the second impurity region. The dummy contact includes a plurality of long contacts arranged in the second direction.

公开(公告)号：US20240313066A1

公开(公告)日：2024-09-19

申请号：US18409031

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo Kyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: H01L29/40 ,  G03F7/00 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/401 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  G03F7/2004 ,  G03F7/2022 ,  G03F7/7045

Abstract: A method of fabricating a semiconductor device may include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit line structure on the cell region, forming a preliminary conductive layer to cover the bit line structure and the peripheral gate structure, and etching the preliminary conductive layer to form a landing pad and peripheral conductive pads. The etching of the preliminary conductive layer may include forming lower and photoresist layers on the preliminary conductive layer, performing a first exposure process on the photoresist layer, performing a second exposure process on the photoresist layer, and etching the preliminary conductive layer using the photoresist and lower layers as an etch mask. The first exposure process may expose a portion of the photoresist layer that is on the cell region to light.