公开(公告)号：US20190065392A1

公开(公告)日：2019-02-28

申请号：US15684252

申请日：2017-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Elona EREZ ,  Avner DOR ,  Moshe TWITTO ,  Jun Jin KONG

IPC: G06F12/1009 ,  G06F12/02

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

公开(公告)号：US20170139769A1

公开(公告)日：2017-05-18

申请号：US14941051

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Evgeny BLAICHMAN ,  Moshe TWITTO ,  Avner DOR ,  Elona EREZ ,  Jun Jin KONG ,  Shay LANDIS ,  Yaron SHANY ,  Yoav SHERESHEVSKI

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/098 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2948 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/455

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

公开(公告)号：US20170024278A1

公开(公告)日：2017-01-26

申请号：US14808505

申请日：2015-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moshe TWITTO ,  Jun-Jin KONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory controller of a memory system, the memory system including the memory controller and a memory device, includes a processor configured to receive write data an control the memory controller; and an encoder, the processor being configured to, receive write data, read previously programmed data from a first memory page of a memory cell array of the memory device, and control the encoder to generate encoded data by encoding the write data using stuck bit code (SBC), based on the read previously programmed data, the previously programmed data being data that has been programmed into the first memory page of the memory cell array and has not been erased; the processor being configured to write the encoded data to the first memory page without erasing the first memory page.

Abstract translation: 存储器系统的存储器控​​制器，包括存储器控制器和存储器件的存储器系统，包括：处理器，被配置为接收写入数据，控制存储器控制器; 以及编码器，所述处理器被配置为接收写入数据，从所述存储器件的存储器单元阵列的第一存储器页面读取先前编程的数据，并且通过使用卡位位代码对写入数据进行编码来控制编码器生成编码数据 （SBC），基于读取的先前编程的数据，先前编程的数据是已被编程到存储器单元阵列的第一存储器页面中并且尚未被擦除的数据; 处理器被配置为将编码数据写入第一存储器页，而不擦除第一存储器页。

公开(公告)号：US20150149859A1

公开(公告)日：2015-05-28

申请号：US14542828

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moshe TWITTO ,  Avner DOR ,  Jun Jin KONG ,  Jung Soo CHUNG

IPC: G06F11/10

CPC classification number: G06F11/1012 ,  G06F11/108 ,  G06F2211/109 ,  H03M13/036 ,  H03M13/1157 ,  H03M13/118 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/611

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information, regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells, in a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract translation: 示例性实施例公开了用于在存储器系统中对数据进行编码和解码的方法和装置。 在根据本发明构思的示例性实施例的编码方法中，基于所存储的数据和辅助数据的组合，根据被卡住的小区和基于关于被卡小区的坐标的信息的编码矩阵来生成码字， 卡住的细胞。 在根据本发明构思的示例性实施例的解码方法中，生成的码字包括对应于与被卡住的小区的坐标对应的地址处的卡住的小区的值的数据，可以通过将编码矩阵的逆矩阵相乘来生成数据 用于编码码字。

公开(公告)号：US20150058692A1

公开(公告)日：2015-02-26

申请号：US14334947

申请日：2014-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Amir BENNATAN ,  Avner DOR ,  Moshe TWITTO ,  Guy GABSO ,  Yoav SHERESHEVSKI ,  Uri BEITLER ,  Jun-jin KONG ,  Beom-Kyu SHIN

IPC: H03M13/11

CPC classification number: H03M13/1111 ,  G11B2020/185 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/6566

Abstract: A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph.

Abstract translation: 低密度奇偶校验（LDPC）解码方法包括基于表示在校验节点和可变节点之间交换消息的顺序的调度信息进行LDPC解码的校验节点和可变节点之间的消息交换，并且基于LDPC解码 在所交换的消息上，其中通过在LDPC二分图中操纵校验节点的顺序和可变节点的顺序中的至少一个来确定调度信息。

公开(公告)号：US20130205075A1

公开(公告)日：2013-08-08

申请号：US13756784

申请日：2013-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moshe TWITTO ,  Rutie ADAR ,  Shay LANDIS

IPC: G11C16/26 ,  G06F12/02 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F12/0246 ,  G11C5/141 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/3431 ,  G11C16/3459

Abstract: There is provided a nonvolatile memory device including a memory cell array including nonvolatile memory cells, a battery not supplied with external power and configured to store a charged voltage, a sensing unit configured to sense a degradation state of the nonvolatile memory cells of the memory cell array, and a trigger circuit configured to transmit a refresh trigger signal based on the sensing result, wherein the nonvolatile memory cells of the memory cell array are refreshed using the charged voltage provided by the battery in response to the trigger signal transmitted from the trigger circuit.

Abstract translation: 提供一种包括非易失性存储单元的存储单元阵列，未被提供外部电源并被配置为存储充电电压的电池的非易失性存储器件，被配置为感测存储单元的非易失性存储单元的劣化状态的感测单元 阵列和触发电路，其被配置为基于所述感测结果发送刷新触发信号，其中所述存储单元阵列的非易失性存储单元响应于从所述触发电路发送的触发信号，使用由所述电池提供的充电电压来刷新 。