公开(公告)号：US11778835B2

公开(公告)日：2023-10-03

申请号：US17723523

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H10B51/00

CPC classification number: H10B51/30 ,  H01L29/511 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/00

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US11387236B2

公开(公告)日：2022-07-12

申请号：US16840880

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Jaeyeol Song ,  Wandon Kim ,  Byounghoon Lee ,  Musarrat Hasan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

公开(公告)号：US12133393B2

公开(公告)日：2024-10-29

申请号：US17502380

申请日：2021-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do Young Choi ,  Kab Jin Nam ,  In Bong Pok ,  Dae Won Ha ,  Musarrat Hasan

IPC: H01L27/11592 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/40 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/40111 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H10B51/30

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

公开(公告)号：US11335701B2

公开(公告)日：2022-05-17

申请号：US16780006

申请日：2020-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US20240381627A1

公开(公告)日：2024-11-14

申请号：US18419907

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Musarrat Hasan ,  Byounghoon Lee ,  Sukhoon Kim ,  Eulji Jeong

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including an NMOS region and a PMOS region, a first gate electrode inside the substrate in the NMOS region, and a second gate electrode inside the substrate in the PMOS region. The first gate electrode includes a first electrode pattern, and the second gate electrode includes a second electrode pattern. The first gate electrode further includes a first N-type conductive pattern between the first electrode pattern and the substrate. The second gate electrode further includes a P-type conductive pattern between the second electrode pattern and the substrate, and the P-type conductive pattern includes molybdenum titanium nitride (MoTiN) or molybdenum silicon nitride (MoSiN).

公开(公告)号：US20230165012A1

公开(公告)日：2023-05-25

申请号：US18049366

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gabjin Nam ,  Bongjin Kuh ,  Musarrat Hasan ,  Geonju Park ,  Yongho Ha

IPC: H01L27/1159

CPC classification number: H01L27/1159

Abstract: A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.

公开(公告)号：US20210035989A1

公开(公告)日：2021-02-04

申请号：US16780006

申请日：2020-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US20240395615A1

公开(公告)日：2024-11-28

申请号：US18631548

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokwon Kim ,  Bongjin Kuh ,  Sukhoon Kim ,  Jiho Park ,  Sanghyeok Yu ,  Yongho Ha ,  Musarrat Hasan

IPC: H01L21/768 ,  C23C16/34 ,  C23C16/505

Abstract: A method of manufacturing a semiconductor device includes forming a substrate including a structure having a first region and a contact hole exposing the first region, loading the substrate into a process chamber, repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first time duration and not applying the RF plasma power to the process gas for a second time duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, and thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure, performing a removal process of removing at least a portion of the sidewall material layer in the process chamber, and unloading the substrate from the process chamber after performing the removal process.

公开(公告)号：US12062661B2

公开(公告)日：2024-08-13

申请号：US17831861

申请日：2022-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Jaeyeol Song ,  Wandon Kim ,  Byounghoon Lee ,  Musarrat Hasan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

公开(公告)号：US20230403861A1

公开(公告)日：2023-12-14

申请号：US18453483

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H10B51/00

CPC classification number: H10B51/30 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/511 ,  H10B51/00

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.