公开(公告)号：US20190214498A1

公开(公告)日：2019-07-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20150031183A1

公开(公告)日：2015-01-29

申请号：US14485035

申请日：2014-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Abstract translation: 通过在包括硅和锗或锗的外延区域上生长硅来制造具有硅化物源极/漏极区的半导体器件。 在该方法中，在半导体衬底上形成有栅极绝缘层的栅电极。 在栅极两侧的半导体衬底中形成外延层。 形成硅层来覆盖外延层。 硅层和金属材料反应形成硅化物层。 在PMOS中，外延层具有暴露在有源区的上表面上方的顶表面和倾斜侧表面。 硅层在外延层上生长，以覆盖顶部和倾斜表面。

公开(公告)号：US08906761B2

公开(公告)日：2014-12-09

申请号：US13798700

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhye Kim ,  Sangho Rha ,  Jeong-Kyu Lee ,  Zulkarnain ,  Kyungseok Oh ,  Sangbom Kang ,  Seungjae Lee ,  Jungchan Lee

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material.

Abstract translation: 使用可膨胀材料制造半导体器件。 该方法包括在衬底上形成第一栅极绝缘层，在第一栅极绝缘层上形成第一和第二栅极结构，第一和第二栅极结构彼此间隔一定距离，在侧壁和上部形成可膨胀材料 第一和第二栅极结构的表面，在第一和第二栅极结构之间的可膨胀材料上形成间隙填充层，并且执行热处理工艺以增加可膨胀材料的体积。

公开(公告)号：US08772115B2

公开(公告)日：2014-07-08

申请号：US13770709

申请日：2013-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HyeokJun Son ,  Sangjin Hyun ,  Sangbom Kang ,  SungKee Han ,  Sughun Hong ,  Hyung-seok Hong

IPC: H01L21/8238

CPC classification number: H01L21/823857

Abstract: A semiconductor device including a selectively nitrided gate insulating layer may be fabricated by a method that includes forming a first gate insulating layer on a substrate having a first region and a second region, performing a nitridation process on the first gate insulating layer, removing the first gate insulating layer from at least a portion of the first region to expose at least a portion of the substrate, forming a second gate insulating layer on at least the exposed portion of the first region of the substrate, thermally treating the first and second gate insulating layers in an oxygen atmosphere, forming a high-k dielectric on the first and second gate insulating layers, and forming a metal gate electrode on the high-k dielectric.

Abstract translation: 可以通过包括在具有第一区域和第二区域的衬底上形成第一栅极绝缘层的方法来制造包括选择性氮化栅极绝缘层的半导体器件，在第一栅极绝缘层上进行氮化处理，去除第一栅极绝缘层 栅极绝缘层，以从第一区域的至少一部分露出至少一部分基板，在至少基板的第一区域的暴露部分上形成第二栅极绝缘层，热处理第一和第二栅极绝缘层 层，在第一和第二栅极绝缘层上形成高k电介质，并在高k电介质上形成金属栅电极。

公开(公告)号：US11004976B2

公开(公告)日：2021-05-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10263109B2

公开(公告)日：2019-04-16

申请号：US14995215

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20140073125A1

公开(公告)日：2014-03-13

申请号：US13798700

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhye Kim ,  Sangho Rha ,  Jeong-Kyu Lee ,  Zulkarnain ,  Kyungseok Oh ,  Sangbom Kang ,  Seungjae Lee ,  Jungchan Lee

IPC: H01L29/66

CPC classification number: H01L29/66666 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device is manufactured using an expandable material. The method includes forming a first gate insulating layer on a substrate, forming first and second gate structures on the first gate insulating layer, the first and second gate structures being spaced apart from each other at a distance, forming an expandable material on sidewalls and upper surfaces of the first and second gate structures, forming a gap-fill layer on the expandable material between the first and second gate structures, and performing a heat-treatment process to increase the volume of the expandable material.

Abstract translation: 使用可膨胀材料制造半导体器件。 该方法包括在衬底上形成第一栅极绝缘层，在第一栅极绝缘层上形成第一和第二栅极结构，第一和第二栅极结构彼此间隔一定距离，在侧壁和上部形成可膨胀材料 第一和第二栅极结构的表面，在第一和第二栅极结构之间的可膨胀材料上形成间隙填充层，并且执行热处理工艺以增加可膨胀材料的体积。

公开(公告)号：US10170622B2

公开(公告)日：2019-01-01

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20170278967A1

公开(公告)日：2017-09-28

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20160133748A1

公开(公告)日：2016-05-12

申请号：US14995215

申请日：2016-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.