公开(公告)号：US12087388B2

公开(公告)日：2024-09-10

申请号：US17504918

申请日：2021-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Soo Yu ,  Namsung Kim ,  Kyomin Sohn ,  Seongil O ,  Sukhan Lee

IPC: G11C7/10 ,  G11C5/02 ,  G11C11/408 ,  G11C11/409

CPC classification number: G11C7/1045 ,  G11C5/025 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/409

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US11567692B2

公开(公告)日：2023-01-31

申请号：US17213732

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongil O ,  Jongpil Son ,  Kyomin Sohn

IPC: G06F3/06

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

公开(公告)号：US20220100467A1

公开(公告)日：2022-03-31

申请号：US17547991

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

公开(公告)号：US20210407577A1

公开(公告)日：2021-12-30

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20210263671A1

公开(公告)日：2021-08-26

申请号：US17009992

申请日：2020-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Kyomin Sohn

IPC: G06F3/06 ,  H01L25/065

Abstract: A stacked memory device includes a plurality memory semiconductor dies, a plurality of through silicon vias, a function-in-memory (FIM) front-end circuit and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor dies are stacked on the buffer semiconductor die, and include a plurality of memory banks. The through-silicon vias electrically connect the buffer semiconductor die and the memory semiconductor dies. The FIM front-end circuit receives a plurality of FIM instructions for a FIM operation from the host device, and stores the FIM instructions. The FIM operation includes data processing based on internal data read from the memory banks. The FIM back-end circuits are respectively included in the memory semiconductor dies. The FIM back-end circuits perform the FIM operation corresponding to the plurality of FIM instructions stored in the FIM front-end circuit under control of the FIM front-end circuit.

公开(公告)号：US11822898B2

公开(公告)日：2023-11-21

申请号：US17547991

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F7/48 ,  G06F13/16 ,  G11C7/1048 ,  G11C2207/2272

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

公开(公告)号：US11763876B2

公开(公告)日：2023-09-19

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C8/12 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/4087 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US11635962B2

公开(公告)日：2023-04-25

申请号：US16814462

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhan Lee ,  Shinhaeng Kang ,  Namsung Kim ,  Seongil O ,  Hak-Soo Yu

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US11550543B2

公开(公告)日：2023-01-10

申请号：US16691033

申请日：2019-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Seongil O

IPC: G06F7/48 ,  G06F13/16 ,  G11C7/10

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

公开(公告)号：US11355181B2

公开(公告)日：2022-06-07

申请号：US17333366

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung Kim ,  Sukhan Lee

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.