MEMORY COMPRESSION METHOD OF ELECTRONIC DEVICE AND APPARATUS THEREOF
    1.
    发明申请
    MEMORY COMPRESSION METHOD OF ELECTRONIC DEVICE AND APPARATUS THEREOF 审中-公开
    电子设备的记忆压缩方法及其装置

    公开(公告)号:US20150339059A1

    公开(公告)日:2015-11-26

    申请号:US14436344

    申请日:2014-10-20

    Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

    Abstract translation: 公开了一种电子设备的记忆压缩方法及其装置。 用于压缩电子设备中的存储器的方法可以包括:检测执行第一应用的请求; 确定所述存储器压缩是否需要用于执行所述第一应用; 当需要存储器压缩时,在电子设备的背景中对与应用程序相对应的存储器进行压缩; 并执行第一应用。

    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSORS
    3.
    发明申请
    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR IMAGE SENSORS 审中-公开
    补充金属氧化物半导体图像传感器

    公开(公告)号:US20170040365A1

    公开(公告)日:2017-02-09

    申请号:US15298204

    申请日:2016-10-19

    Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor is provided. The CMOS image sensor may include an epitaxial layer having a first conductivity type and having first and second surfaces, a first device isolation layer extending from the first surface to the second surface to define first and second pixel regions, a well impurity layer of a second conductivity type formed adjacent to the first surface and formed in the epitaxial layer of each of the first and second pixel regions, and a second device isolation layer formed in the well impurity layer in each of the first and second pixel regions to define first and second active portions spaced apart from each other in each of the first and second pixel regions.

    Abstract translation: 提供了互补的金属氧化物半导体(CMOS)图像传感器。 CMOS图像传感器可以包括具有第一导电类型并具有第一和第二表面的外延层,从第一表面延伸到第二表面以限定第一和第二像素区域的第一器件隔离层,第二和第二表面的阱杂质层 导电类型,形成在第一表面附近并形成在第一和第二像素区域中的每一个的外延层中,以及第二器件隔离层,形成在第一和第二像素区域中的每一个中的阱杂质层中,以限定第一和第二像素区域 在第一和第二像素区域中的每一个中彼此间隔开的有源部分。

    SEMICONDUCTOR DEVICE
    4.
    发明公开

    公开(公告)号:US20230290838A1

    公开(公告)日:2023-09-14

    申请号:US18181071

    申请日:2023-03-09

    CPC classification number: H01L29/405 H01L29/41791 H01L29/7851

    Abstract: A semiconductor device includes a substrate including an active region, a first gate line and a second gate line in the active region, a first source/drain contact pattern in the active region at one side of the first gate line, a second source/drain contact pattern in the active region at one side of the second gate line, and a dummy source/drain contact pattern in the active region between the first gate line and the second gate line. The first gate line and the second gate line may be spaced apart from each other in the first direction and may extend in the second direction. The second direction may cross the first direction. A size of the dummy source/drain contact pattern may be less than a size of the first source/drain contact pattern and a size of the second source/drain contact pattern.

    IMAGE SENSORS
    5.
    发明申请

    公开(公告)号:US20220336506A1

    公开(公告)日:2022-10-20

    申请号:US17667620

    申请日:2022-02-09

    Inventor: Seungwook LEE

    Abstract: Image sensors may include a base substrate including a substrate layer, a buried insulation layer on the substrate layer, and a semiconductor layer on the buried insulation layer, a photo sensing device in the substrate layer, a buried impurity region spaced apart from the photo sensing device in an upper portion of the substrate layer, a transfer gate including a vertical gate extending through the semiconductor layer and the buried insulation layer and extending into an inner portion of the substrate layer, which is between the photo sensing device and the buried impurity region, a planar gate on the semiconductor layer, and a gate insulation layer between the substrate layer and the planar gate.

    ELECTRONIC SYSTEM INCLUDING FPGA AND OPERATION METHOD THEREOF

    公开(公告)号:US20210250028A1

    公开(公告)日:2021-08-12

    申请号:US17242737

    申请日:2021-04-28

    Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

    IMAGE SENSORS
    8.
    发明申请

    公开(公告)号:US20250031464A1

    公开(公告)日:2025-01-23

    申请号:US18906999

    申请日:2024-10-04

    Inventor: Seungwook LEE

    Abstract: Image sensors may include a base substrate including a substrate layer, a buried insulation layer on the substrate layer, and a semiconductor layer on the buried insulation layer, a photo sensing device in the substrate layer, a buried impurity region spaced apart from the photo sensing device in an upper portion of the substrate layer, a transfer gate including a vertical gate extending through the semiconductor layer and the buried insulation layer and extending into an inner portion of the substrate layer, which is between the photo sensing device and the buried impurity region, a planar gate on the semiconductor layer, and a gate insulation layer between the substrate layer and the planar gate.

Patent Agency Ranking