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公开(公告)号：US20230147765A1
公开(公告)日：2023-05-11
申请号：US17953715
申请日：2022-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungyeon Kim , Jooyong Park , Hongsoo Jeon
IPC: G11C11/4099 , G11C11/4097 , G11C11/408
CPC classification number: G11C11/4099 , G11C11/4097 , G11C11/4085 , G11C11/4087
Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
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公开(公告)号：US10114414B2
公开(公告)日：2018-10-30
申请号：US15861316
申请日：2018-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Hwan Lee , Jin Yong Kim , Hyungwoo Lee , Seungyeon Kim , You-Sub Shim , Jong-Chul Choi
IPC: G06F1/16 , H05K5/00 , H05K7/00 , H01Q1/22 , G04G17/04 , G06F3/14 , G04R60/12 , H01Q1/27 , G06F3/01
Abstract: An electronic device includes a housing including a first plate, a second plate, and a side member a first band detachably mounted to the side member, and shaped to wrap around a wrist of a user; a display exposed through the first plate; a processor a memory and a mounting structure configured to connect the first band to the side member. The mounting structure includes a recessed structure formed in the side member, the recessed structure having a first surface, a second surface, a first hole formed in the first surface, and a second hole formed in the second surface, and facing the first hole, in which an imaginary line extending from the first hole to the second hole defines a first axis; a rotating member positioned to rotate around the first axis, the rotating member having a through-hole that has an inner screw surface centered around the first axis; a first rod extending along the first axis through a first portion of the first band, in which the first rod has a first end inserted into the first hole, and a second end held by the rotating member such that the first rod does not move along the first axis while the rotating member rotates; and a second rod extending along the first axis through a second portion of the first band. The second rod has: a third end rotatably inserted into the second hole; and an external screw surface engaged with the inner screw surface of the rotating member such that the second rod moves along the first axis while the rotating member rotates.
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公开(公告)号：US20180188772A1
公开(公告)日：2018-07-05
申请号：US15861316
申请日：2018-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Hwan LEE , Jin Yong Kim , Hyungwoo Lee , Seungyeon Kim , You-Sub Shim , Jong-Chul CHOI
CPC classification number: G06F1/163 , A44C5/14 , G04B37/1486 , G04G17/045 , G04R60/12 , G06F3/016 , G06F3/14 , H01Q1/22 , H01Q1/273
Abstract: An electronic device includes a housing including a first plate, a second plate, and a side member a first band detachably mounted to the side member, and shaped to wrap around a wrist of a user; a display exposed through the first plate; a processor a memory and a mounting structure configured to connect the first band to the side member. The mounting structure includes a recessed structure formed in the side member, the recessed structure having a first surface, a second surface, a first hole formed in the first surface, and a second hole formed in the second surface, and facing the first hole, in which an imaginary line extending from the first hole to the second hole defines a first axis; a rotating member positioned to rotate around the first axis, the rotating member having a through-hole that has an inner screw surface centered around the first axis; a first rod extending along the first axis through a first portion of the first band, in which the first rod has a first end inserted into the first hole, and a second end held by the rotating member such that the first rod does not move along the first axis while the rotating member rotates; and a second rod extending along the first axis through a second portion of the first band. The second rod has: a third end rotatably inserted into the second hole; and an external screw surface engaged with the inner screw surface of the rotating member such that the second rod moves along the first axis while the rotating member rotates.
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公开(公告)号：US12198753B2
公开(公告)日：2025-01-14
申请号：US17953715
申请日：2022-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungyeon Kim , Jooyong Park , Hongsoo Jeon
IPC: G11C7/02 , G11C11/408 , G11C11/4097 , G11C11/4099
Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
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公开(公告)号：US20240049481A1
公开(公告)日：2024-02-08
申请号：US18188311
申请日：2023-03-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungyeon Kim , Takuya Futatsuyama , Jooyong Park , Beakhyung Cho
IPC: H10B80/00
CPC classification number: H10B80/00
Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction and word lines each extending in a second direction and stacked in a vertical direction, word line pads which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width in the first direction and a second width in the second direction. Each of the pass transistors has a first pitch in the first direction and a second pitch in the second direction.
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Patent Agency Ranking
公开(公告)号：US20250104764A1
公开(公告)日：2025-03-27
申请号：US18972079
申请日：2024-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungyeon Kim , Jooyong Park , Hongsoo Jeon
IPC: G11C11/4099 , G11C11/408 , G11C11/4097
Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
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公开(公告)号：US20240071517A1
公开(公告)日：2024-02-29
申请号：US18504093
申请日：2023-11-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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公开(公告)号：US20240065004A1
公开(公告)日：2024-02-22
申请号：US18366723
申请日：2023-08-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jooyong Park , Seungyeon Kim , Daeseok Byeon
CPC classification number: H10B80/00 , H10B43/27 , H10B43/35 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.
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公开(公告)号：US11887672B2
公开(公告)日：2024-01-30
申请号：US17693013
申请日：2022-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myeong-Woo Lee , Seungyeon Kim , Dongha Shin , Beakhyung Cho
CPC classification number: G11C16/16 , G11C7/1039 , G11C16/24 , G11C16/28 , G11C16/30
Abstract: A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.
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公开(公告)号：US11837293B2
公开(公告)日：2023-12-05
申请号：US17898885
申请日：2022-08-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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