公开(公告)号：US09711188B2

公开(公告)日：2017-07-18

申请号：US15141967

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Jae-Hun Jeong ,  Ki-Hyun Kim

IPC: H01L27/112 ,  G11C5/06 ,  H01L27/115 ,  H01L27/11517

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

公开(公告)号：US12207471B2

公开(公告)日：2025-01-21

申请号：US17459887

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae-Min Lee ,  Kwang-Soo Kim ,  Sun-Il Shim

IPC: H10B43/35 ,  G11C5/06 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

公开(公告)号：US11171151B2

公开(公告)日：2021-11-09

申请号：US16354448

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan Kang ,  Sun-Il Shim ,  Seung Hyun

IPC: H01L23/535 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/45 ,  H01L27/11573

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US11062784B2

公开(公告)日：2021-07-13

申请号：US16844317

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20210295895A1

公开(公告)日：2021-09-23

申请号：US17342048

申请日：2021-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C5/06

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US08952438B2

公开(公告)日：2015-02-10

申请号：US13901205

申请日：2013-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract translation: 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

公开(公告)号：US12048156B2

公开(公告)日：2024-07-23

申请号：US17450726

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan Kang ,  Sun-Il Shim ,  Seung Hyun

IPC: H10B43/27 ,  H01L23/535 ,  H01L29/423 ,  H01L29/45 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H01L29/4234 ,  H01L29/456 ,  H10B43/40

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US11715537B2

公开(公告)日：2023-08-01

申请号：US17542183

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/34 ,  G11C16/04 ,  H10B43/27 ,  G11C16/08 ,  G11C16/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  H10B43/35

CPC classification number: G11C16/3459 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H10B43/27 ,  H10B43/35

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US10650903B2

公开(公告)日：2020-05-12

申请号：US16206383

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US09966115B2

公开(公告)日：2018-05-08

申请号：US15586002

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Jae-Hun Jeong ,  Ki-Hyun Kim

IPC: H01L27/115 ,  G11C5/06 ,  H01L23/528

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.