公开(公告)号：US12288578B2

公开(公告)日：2025-04-29

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Byeonggyu Park ,  Yeonggeol Song

IPC: G11C11/406 ,  G11C11/4093

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20240385925A1

公开(公告)日：2024-11-21

申请号：US18543737

申请日：2023-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu Lee ,  Seongmuk Kang ,  Daehyun Kim ,  Jiho Kim ,  Kyomin Sohn ,  Kijun Lee ,  Sunghye Cho

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/07

Abstract: A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller includes a plurality of volatile memory devices; and a memory controller configured to control the plurality of volatile memory devices, wherein the memory controller includes: a host interface configured to communicate with a host device based on a Compute eXpress Link (CXL) communication protocol; an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level being error correction levels based on cell reliability information and data reliability request information which are associated with the cache line data; and an ECC engine configured to, based on the ECC control signal indicating the first correction level, generate first parity symbols associated with the cache line data, and based on the ECC control signal indicating the second correction level, generate additional parity symbols.

公开(公告)号：US20230178168A1

公开(公告)日：2023-06-08

申请号：US18164100

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2029/1204

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US11656935B2

公开(公告)日：2023-05-23

申请号：US17351619

申请日：2021-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguhn Cha ,  Hoyoung Song ,  Myungkyu Lee ,  Sunghye Cho

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/406 ,  G06F11/30

CPC classification number: G06F11/106 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F13/1673 ,  G11C11/4082 ,  G11C11/40615

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.

公开(公告)号：US20230119555A1

公开(公告)日：2023-04-20

申请号：US17736154

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/11

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

公开(公告)号：US12236991B1

公开(公告)日：2025-02-25

申请号：US18188256

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunae Lee ,  Sunghye Cho ,  Kijun Lee ,  Junjin Kong ,  Yeonggeol Song

IPC: G11C11/406 ,  G06F12/06 ,  G11C11/408

Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

公开(公告)号：US12176919B2

公开(公告)日：2024-12-24

申请号：US17988140

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Jin-Hoon Jang ,  Isak Hwang

IPC: H03M13/00 ,  G11C29/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

公开(公告)号：US20240339168A1

公开(公告)日：2024-10-10

申请号：US18746565

申请日：2024-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C11/4087 ,  G11C11/4091 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US11947810B2

公开(公告)日：2024-04-02

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US11860734B2

公开(公告)日：2024-01-02

申请号：US17736154

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048 ,  H03M13/1108

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.