公开(公告)号：US11887968B2

公开(公告)日：2024-01-30

申请号：US17493975

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong ,  Tae Hun Kim ,  Hyuek Jae Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

公开(公告)号：US11466867B2

公开(公告)日：2022-10-11

申请号：US16720869

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Hun Kim ,  Hyun Sang Kim ,  Bok Hyun Jang ,  Yu Jeub Ha ,  Qasim Khan

IPC: F24C15/32 ,  F24C14/02 ,  F24C3/08 ,  A21B1/26 ,  F24C14/00 ,  A47J27/00 ,  F24C15/02 ,  A21B3/02

Abstract: An oven with an enhanced structure to keep a cooking space clean includes a main body, a cooking chamber formed inside the main body and including a bottom wall, a burner provided at an outer lower part of the cooking chamber to heat up the cooking chamber, a door arranged to open or close the cooking chamber, a bottom plate coupled to the bottom wall of the cooking chamber with a gap from the bottom wall such that the bottom plate is located inside the cooking chamber, and an outlet for heated air formed between one end of the bottom plate facing the door and the bottom wall of the cooking chamber such that heated air generated from the burner is supplied to the door.

公开(公告)号：US20210296228A1

公开(公告)日：2021-09-23

申请号：US17338815

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US10978618B2

公开(公告)日：2021-04-13

申请号：US17005643

申请日：2020-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JuHeon Yoon ,  Jung Hwan Kil ,  Tae Hun Kim ,  Hwa Ryong Song ,  Jae In Sim

IPC: H01L33/40 ,  H01L33/06 ,  H01L33/12 ,  H01L33/22 ,  H01L33/50 ,  H01L33/60 ,  H01L33/62 ,  H01L33/42 ,  H01L33/46

Abstract: A semiconductor light emitting device includes a light emitting structure having a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer, a transparent electrode layer on the second conductivity-type semiconductor layer and spaced apart from an edge of the second conductivity-type semiconductor layer, a first insulating layer on the light emitting structure to cover the transparent electrode layer and including a plurality of holes connected to the transparent electrode layer, and a reflective electrode layer on the first insulating layer and connected to the transparent electrode layer through the plurality of holes.

公开(公告)号：US10971470B2

公开(公告)日：2021-04-06

申请号：US16511695

申请日：2019-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Chul Kim ,  Tae Hun Kim ,  Ji Hwan Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.

公开(公告)号：US10656671B2

公开(公告)日：2020-05-19

申请号：US16425171

申请日：2019-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Bong Kim ,  Tae Hun Kim ,  Yong Gu Do ,  Gil Jae Lee ,  Pil Kwon Jung

IPC: G06F1/16 ,  H05K5/02 ,  H05K5/00 ,  F16M11/24

Abstract: Provided is a display device including a display panel configured to display an image forward. The display device includes a top chassis arranged on the front of the display panel; a bottom chassis arranged on the back of the display panel; a rear cover covering the back of the bottom chassis; and a stand unit including a stand provided to support the display device, a locking device provided to lock the stand to be pulled in between the bottom chassis and the rear cover, and a rotation guide provided to rotate at least a portion of the stand, wherein the rear cover includes a through hole formed for the stand to move vertically, and the stand is locked in the locking device and pulled in between the bottom chassis and the rear cover, or the stand is pulled out of the display device through the through hole.

公开(公告)号：US11887900B2

公开(公告)日：2024-01-30

申请号：US17367903

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Tae Hun Kim ,  Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong

IPC: H01L23/528 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/5283 ,  H01L24/09

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

公开(公告)号：US11581257B2

公开(公告)日：2023-02-14

申请号：US17338815

申请日：2021-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuek Jae Lee ,  Ji Hoon Kim ,  Tae Hun Kim ,  Ji Seok Hong ,  Ji Hwan Hwang

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

公开(公告)号：US11227870B2

公开(公告)日：2022-01-18

申请号：US16739392

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US11165018B2

公开(公告)日：2021-11-02

申请号：US16592041

申请日：2019-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Tae Hun Kim ,  Seok Han Park ,  Satoru Yamada ,  Jae Ho Hong

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.