公开(公告)号：US20220374038A1

公开(公告)日：2022-11-24

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/08

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

公开(公告)号：US11927981B2

公开(公告)日：2024-03-12

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

公开(公告)号：US12079491B2

公开(公告)日：2024-09-03

申请号：US18150626

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewoo Han ,  Wooil Kim ,  Taehun Kim

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

公开(公告)号：US20230266893A1

公开(公告)日：2023-08-24

申请号：US18150626

申请日：2023-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewoo Han ,  Wooil Kim ,  Taehun Kim

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

公开(公告)号：US12174683B2

公开(公告)日：2024-12-24

申请号：US17956195

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhee Yoo ,  Jaehyun Kim ,  Jingyu Ahn ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/3234 ,  G11C7/22

Abstract: A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

公开(公告)号：US11663131B2

公开(公告)日：2023-05-30

申请号：US17374076

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongmin Jo ,  Youngseok Kim ,  Chunghwan You ,  Wooil Kim

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F2212/68

Abstract: An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.

公开(公告)号：US11302384B2

公开(公告)日：2022-04-12

申请号：US16931933

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulung Kim ,  Joungyeal Kim ,  Seongheon Yu ,  Hyunjin Ko ,  Wooil Kim ,  Hyeonsoo Sim

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F13/40 ,  G06F13/16 ,  H01L25/065 ,  H01L25/18

Abstract: In a method of controlling on-die termination (ODT) in a memory system including a plurality of memory units that shares a data bus to transfer data, ODT circuits of the plurality of memory units are enabled into an initial state, a resistance value of the ODT circuit is set to a first resistance value, of at least one write non-target memory unit among the plurality of memory units during a write operation on a write target memory unit among the plurality of memory units, and a resistance value of the ODT circuit is set to a second resistance value, of at least one read non-target memory unit among the plurality of memory units during a read operation on a read target memory unit among the plurality of memory units.