公开(公告)号：US10373975B2

公开(公告)日：2019-08-06

申请号：US16162720

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US10128263B2

公开(公告)日：2018-11-13

申请号：US15224238

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US20250079265A1

公开(公告)日：2025-03-06

申请号：US18457311

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo Le ,  Min Chan Gwak ,  Guk Hee Kim ,  Beom Jin Kim ,  Young Woo Kim ,  Anthony Dongick Lee ,  Myeong Gyoon Chae

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate that includes a first surface and a second surface, a first source/drain pattern disposed on the first surface of the substrate, a second source/drain pattern disposed on the first surface of the, a first source/drain contact disposed on the first source/drain pattern and connected to the first source/drain pattern, a second source/drain contact disposed on the second source/drain pattern and connected to the second source/drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source/drain contact, a second contact connection via that connects the rear wiring line with the second source/drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

公开(公告)号：US20240282829A1

公开(公告)日：2024-08-22

申请号：US18500797

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Woo Kim ,  Kyoung Woo Lee ,  Min Chan Gwak ,  Guk Hee Kim ,  Sang Cheol Na ,  Anthony Dongick Lee

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate that has first and second surfaces opposite to each other in a first direction, a first fin-type pattern that protrudes in the first direction from the first surface of the substrate and extends in a second direction, a first source/drain pattern on the first fin-type pattern, a first source/drain contact on the first source/drain pattern, a contact connection via that extends in the first direction and is electrically connected to the first source/drain contact, a buried conductive pattern that is in the substrate, is electrically connected to the contact connection via, and has first and second surfaces opposite to each other in the first direction, the first surface of the buried conductive pattern facing the first source/drain contact, and first buried insulating liners that extend along sidewalls and along the first surface of the buried conductive pattern.

公开(公告)号：US20190333935A1

公开(公告)日：2019-10-31

申请号：US16506609

申请日：2019-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Cheon BAEK ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/06 ,  H01L27/11568 ,  H01L23/528

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US10916563B2

公开(公告)日：2021-02-09

申请号：US16453094

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Woo Kim ,  Joon Young Kwon ,  Jung Hwan Lee ,  Jung Tae Sung ,  Ji Min Shin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.

公开(公告)号：US20240304513A1

公开(公告)日：2024-09-12

申请号：US18397389

申请日：2023-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick Lee ,  Min Chan Gwak ,  Guk Hee Kim ,  Young Woo Kim ,  Sang Cheol Na ,  Kyoung Woo Lee

IPC: H01L23/367 ,  H01L21/683 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/3672 ,  H01L21/6835 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L2221/68309

Abstract: A semiconductor device includes an active pattern on a first surface of a substrate and extending in a first direction, a field insulating film on the first surface and a side surface of the active pattern, a gate structure on the active pattern and field insulating film and extending in a second direction intersecting the first direction, a source/drain area on a side surface of the gate structure and contacting the active pattern, and a through-contact extending in a third direction perpendicular to the first and second directions and extending through the field insulating film. The device further includes a buried pattern in the substrate contacting the through-contact, a backside wiring structure on a second surface of the substrate and electrically connected to the buried pattern, and a heat-dissipating structure in the substrate adjacent to the buried pattern. The heat-dissipating structure fills a trench extending from the second surface into the substrate.