公开(公告)号：US20240170429A1

公开(公告)日：2024-05-23

申请号：US18346371

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Cha ,  Yunrae Cho

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08052 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2225/06513 ,  H01L2924/3511

Abstract: A semiconductor chip includes a semiconductor substrate that includes an upper surface and a lower surface opposite to the upper surface, a center pad disposed on a center portion of the upper surface and an edge portion disposes on an outer portion of the upper surface; a wiring structure that includes a wiring insulating layer disposed on a lower surface of the semiconductor substrate and a wiring pattern disposed in the wiring insulating layer and electrically connected to the semiconductor substrate; a first bump pad disposed on a first surface of the wiring structure and electrically connected to the wiring pattern; and a first connection bump that connects the first bump pad to an external device. The center pad has a regular octagon shape, and the edge pad has an extended octagon shape formed by extending squares from four non-continuous sides of a regular octagon.

公开(公告)号：US11640951B2

公开(公告)日：2023-05-02

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae Cho ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20230086202A1

公开(公告)日：2023-03-23

申请号：US17839675

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Yoonsung Kim ,  Seungduk Baek ,  Yunrae Cho

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package is provided. The semiconductor package includes, a base structure including a body, an upper pad on the body, and an upper insulating layer on a side surface of the upper pad, the base structure having a planar upper surface provided by the upper insulating layer and the upper pad; and a semiconductor chip on the planar upper surface of the base structure, and including a substrate, a wiring structure below the substrate, a low dielectric layer on a side surface of the wiring structure, a lower connection pad below the wiring structure, and a lower insulating layer on a side surface of the lower connection pad, the semiconductor chip having a planar lower surface provided by the lower insulating layer and the lower connection pad, a side surface provided by the lower insulating layer and the substrate, and a recess surface extending from one end of the side surface to one end of the planar lower surface, wherein the low dielectric layer is spaced apart from the recess surface of the semiconductor chip by the lower insulating layer.

公开(公告)号：US20210057328A1

公开(公告)日：2021-02-25

申请号：US16848246

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US20250132275A1

公开(公告)日：2025-04-24

申请号：US18909082

申请日：2024-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho Cha ,  Yunrae Cho

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a semiconductor substrate, connection pads on a bottom surface of the semiconductor substrate, and connection bumps respectively on the connection pads, wherein the connection bumps include an extension bump and a non-extension bump, wherein the extension bump includes an extension seed layer on a respective one of the connection pads and a first conductive pillar on the extension seed layer, and wherein the extension seed layer longitudinally extends in a first extension direction.

公开(公告)号：US12154881B2

公开(公告)日：2024-11-26

申请号：US18185702

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae Cho ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20230005883A1

公开(公告)日：2023-01-05

申请号：US17857651

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunkeun Kim ,  Yunrae Cho ,  Seungduk Baek

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/13 ,  H01L25/18 ,  H01L23/538

Abstract: A semiconductor package is provided that includes: a package substrate; an interposer mounted on the package substrate; a first semiconductor chip mounted on the interposer; a plurality of second semiconductor chips mounted on the interposer to surround at least a portion of the first semiconductor chip; a heat radiation member arranged on the first semiconductor chip and the plurality of second semiconductor chips; and a heat blocking member extending from a portion of the heat radiation member and arranged in at least one space among a first space between the first semiconductor chip and at least one of the plurality of second semiconductor chips and a second space between at least two of the plurality of second semiconductor chips.

公开(公告)号：US20250149490A1

公开(公告)日：2025-05-08

申请号：US18830785

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee Lee ,  Yunrae Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a plurality of semiconductor chips stacked in a first direction, a plurality of chip connection terminals disposed between two semiconductor chips disposed adjacent to each other in the first direction among the plurality of semiconductor chips and electrically connecting the two adjacent semiconductor chips, and a plurality of chip support structures disposed between the two adjacent semiconductor chips. The plurality of chip support structures do not electrically connect the two adjacent semiconductor chips, and are spaced apart from the plurality of chip connection terminals in a second direction crossing the first direction. A thickness of each of the plurality of chip support structures is greater than a thickness of each of the plurality of chip connection terminals.

公开(公告)号：US12119329B2

公开(公告)日：2024-10-15

申请号：US18448284

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Yunrae Cho ,  Taeheon Kim ,  Seunghun Han

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768 ,  H01L21/78 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/32 ,  H01L23/481 ,  H01L24/14 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/14517 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06596

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

公开(公告)号：US20230230915A1

公开(公告)日：2023-07-20

申请号：US18127342

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/82 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/5222 ,  H01L23/3185 ,  H01L24/05 ,  H01L23/5283 ,  H01L23/481 ,  H01L23/53295 ,  H01L21/76832 ,  H01L23/485 ,  H01L23/5226 ,  H01L21/82 ,  H01L21/561 ,  H01L21/78 ,  H01L23/562 ,  H01L2224/0237 ,  H01L2224/024

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.