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公开(公告)号：US10971199B2
公开(公告)日：2021-04-06
申请号：US16446705
申请日：2019-06-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Pao-Ling Koh , Yuheng Zhang , Yan Li
IPC: G11C7/12 , H03K19/173 , G11C16/26 , G11C16/12
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.
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公开(公告)号：US20200341691A1
公开(公告)日：2020-10-29
申请号：US16909467
申请日：2020-06-23
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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公开(公告)号：US10726921B2
公开(公告)日：2020-07-28
申请号：US15942044
申请日：2018-03-30
Applicant: SanDisk Technologies LLC
Inventor： Chia-Lin Hsiung , Fumiaki Toyama , Tai-Yuan Tseng , Yan Li
IPC: G11C11/34 , G11C16/08 , H01L27/11556 , H01L23/528 , G11C16/04 , H01L27/11582 , G11C11/56
Abstract: A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.
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公开(公告)号：US20200227125A1
公开(公告)日：2020-07-16
申请号：US16829692
申请日：2020-03-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Gerrit Jan Hemink , Tai-Yuan Tseng , Yan Li
Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
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公开(公告)号：US20190179573A1
公开(公告)日：2019-06-13
申请号：US15994116
申请日：2018-05-31
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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Patent Agency Ranking
公开(公告)号：US20190179532A1
公开(公告)日：2019-06-13
申请号：US16003515
申请日：2018-06-08
Applicant: SANDISK TECHNOLOGIES LLC?
Inventor： Tai-Yuan Tseng , Hiroyuki Mizukoshi , Chi-Lin Hsu , Yan Li
Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.
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公开(公告)号：US11699502B2
公开(公告)日：2023-07-11
申请号：US17550352
申请日：2021-12-14
Applicant: SanDisk Technologies LLC
Inventor： Iris Lu , Yan Li , Ohwon Kwon
IPC: G01R31/3181 , G11C29/16 , G11C7/06 , G11C29/54 , H10B80/00 , G01R31/3177 , H01L25/065 , H01L25/18
CPC classification number: G11C29/54 , G01R31/3181 , G11C7/065 , G11C7/067 , G11C29/16 , H10B80/00 , G01R31/3177 , H01L25/065 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18
Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.
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公开(公告)号：US11620050B2
公开(公告)日：2023-04-04
申请号：US17359945
申请日：2021-06-28
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： A Harihara Sravan , Yan Li , Feng Lu
IPC: G06F3/06
Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.
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公开(公告)号：US11011242B2
公开(公告)日：2021-05-18
申请号：US16829692
申请日：2020-03-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Deepanshu Dutta , Gerrit Jan Hemink , Tai-Yuan Tseng , Yan Li
Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
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公开(公告)号：US10725699B2
公开(公告)日：2020-07-28
申请号：US16015624
申请日：2018-06-22
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/32 , G11C16/10 , G11C11/56 , G11C16/26 , G11C16/32 , G11C16/34 , G06F13/00 , G11C16/08 , G11C16/24 , G11C16/04
Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.
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