Abstract:
A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.
Abstract:
An apparatus includes a heat pipe with a fluid path. A first part of the fluid path is thermally coupled to a first region of a higher temperature and a second part of the fluid path thermally is coupled to a second region of a lower temperature. A difference between the higher temperature and the lower temperature induces a flow of a magnetic fluid in the fluid path. A switchable magnetic device is magnetically coupled to the fluid path. Activation of the switchable magnetic device reduces the flow of the magnetic fluid in the fluid path, which reduces heat transfer from the first region to the second region.
Abstract:
A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.
Abstract:
A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is substantially the same as or lower than that of memory cells included in the active list. The memory cells are transferred from the temporary list to the active list in response to satisfaction of a trigger condition.
Abstract:
A memory controller identifies a predominant type of error of a memory unit of solid state memory cells. An error type differential is calculated. The error type differential is a difference between a number of charge loss errors and a number of charge gain errors of the memory unit. A VT offset error differential is calculated. The VT offset error differential is a difference between a number of errors of the predominant type at a first VT offset and a number of errors of the predominant type at a second VT offset. A VT offset is determined using a ratio of the error type differential and the VT offset error differential.
Abstract:
A group of non-volatile, solid state memory cells are transferred from an active list that includes memory cells accessible to a host to a temporary list that includes memory cells temporarily inaccessible to the host. The memory cells included in the temporary list are maintained at a temperature that is substantially the same as or lower than that of memory cells included in the active list. The memory cells are transferred from the temporary list to the active list in response to satisfaction of a trigger condition.
Abstract:
An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about the initial value sufficient to fit a polynomial curve. A minimum is used to determine the lowest bit error rate and corresponding optimum threshold voltage. This voltage is adopted as the new threshold voltage for reading the given data.
Abstract:
An apparatus includes a heat pipe with a fluid path. A first part of the fluid path is thermally coupled to a first region of a higher temperature and a second part of the fluid path thermally is coupled to a second region of a lower temperature. A difference between the higher temperature and the lower temperature induces a flow of a magnetic fluid in the fluid path. A switchable magnetic device is magnetically coupled to the fluid path. Activation of the switchable magnetic device reduces the flow of the magnetic fluid in the fluid path, which reduces heat transfer from the first region to the second region.
Abstract:
Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.
Abstract:
An error of a solid-state non-volatile memory is detected. It is determined whether a type of the error is a first type of error. A voltage recovery process is bypassed based on whether the error is the first type of error. If it is determined that the error is a catastrophic error, the voltage error recovery process is bypassed. If it is determined that an offset of a threshold voltage is not greater than a predetermined value, the voltage error recovery process is bypassed.