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    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
    1.
    发明申请
    CIRCUIT, DRIVING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 审中-公开
    电路，其驱动方法和半导体器件

    公开(公告)号：US20160379564A1

    公开(公告)日：2016-12-29

    申请号：US15183892

    申请日：2016-06-16

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Yoshiyuki KUROKAWA ,  Takashi NAKAGAWA ,  Fumika AKASAWA

    IPC: G09G3/3241

    CPC classification number: G05F3/262 ,  G05F3/26 ,  G09G3/2011 ,  G09G2300/0417 ,  G09G2310/027 ,  G09G2310/0272 ,  G09G2330/021 ,  G11C27/024 ,  H01L27/1225

    Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.

    Abstract translation: 电路包括包括第一和第二晶体管的电流镜电路（CM电路），漏极电连接到第二晶体管的漏极的第三晶体管，控制来自电路的电流输出的开关以及第一和第二存储器电路。 CM电路的参考电流被输入到第一晶体管的漏极; 作为参考电流的副本的电流从第二晶体管的漏极输出。 当从电路输出电流时，参考电流不输入到CM电路。 与存储在第一存储器电路中的电压相对应的漏极电流流过第二晶体管; 与存储在第二存储器电路中的电压相对应的漏极电流流过第三晶体管。 两个漏极电流之间的差值对应于电路的输出电流。

    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE
    2.
    发明公开
    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240364343A1

    公开(公告)日：2024-10-31

    申请号：US18766726

    申请日：2024-07-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Shintaro HARADA ,  Sho NAGAO

    IPC: H03K19/094 ,  H01L27/06

    CPC classification number: H03K19/094 ,  H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    Logic Circuit and Semiconductor Device Formed Using Unipolar Transistor
    3.
    发明申请
    Logic Circuit and Semiconductor Device Formed Using Unipolar Transistor 有权

    公开(公告)号：US20220173737A1

    公开(公告)日：2022-06-02

    申请号：US17441804

    申请日：2020-03-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd

    Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Sho NAGAO

    IPC: H03K19/08 ,  H03K17/56

    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

    MEMORY CIRCUIT USING OXIDE SEMICONDUCTOR
    4.
    发明申请
    MEMORY CIRCUIT USING OXIDE SEMICONDUCTOR 有权

    公开(公告)号：US20220366958A1

    公开(公告)日：2022-11-17

    申请号：US17618993

    申请日：2020-06-09

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Fumika AKASAWA ,  Munehiro KOZUMA

    IPC: G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

    Abstract: Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.

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