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    Wide voltage trans-impedance amplifier
    1.
    发明授权
    Wide voltage trans-impedance amplifier 有权

    公开(公告)号：US11190140B2

    公开(公告)日：2021-11-30

    申请号：US16967745

    申请日：2020-04-30

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Chao Chen ,  Jun Yang ,  Xinning Liu

    IPC: H03F1/02 ,  H03F1/56

    Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.

    Nonlinear disturbance rejection control apparatus and method for electronic throttle control systems
    2.
    发明授权
    Nonlinear disturbance rejection control apparatus and method for electronic throttle control systems 有权

    公开(公告)号：US11168623B2

    公开(公告)日：2021-11-09

    申请号：US16618380

    申请日：2018-11-20

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shihua Li ,  Chen Dai ,  Jun Yang ,  Hao Sun ,  Xiangyu Wang ,  Qi Li

    IPC: F02D41/00 ,  F02D9/10 ,  G05B13/04

    Abstract: A nonlinear disturbance rejection control apparatus and method for electronic throttle control systems are invented to control the electronic throttle system and to achieve a continuous finite-time disturbance rejection control goal. A control sub-apparatus and method are proposed with an observing sub-apparatus and method for controlling the opening angle of an electronic throttle valve. A mathematical model of the electronic throttle system is analyzed and a control-oriented model is presented with the formation of a lumped disturbance. With combination of the continuous terminal sliding mode control method and the output feedback control method, based on the finite-time high-order sliding mode observer, the preferred control performance is guaranteed, where both the dynamic and static performance of the system is effectively improved.

    Bi-directional adaptive clocking circuit supporting a wide frequency range
    3.
    发明授权
    Bi-directional adaptive clocking circuit supporting a wide frequency range 有权

    公开(公告)号：US11139805B1

    公开(公告)日：2021-10-05

    申请号：US16957724

    申请日：2019-07-09

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei Shan ,  Jun Yang ,  Longxing Shi

    IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00 ,  H03K5/00 ,  G06F1/08

    Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

    Process Corner Detection Circuit Based on Self-Timing Oscillation Ring
    6.
    发明申请
    Process Corner Detection Circuit Based on Self-Timing Oscillation Ring 审中-公开

    公开(公告)号：US20170219649A1

    公开(公告)日：2017-08-03

    申请号：US15321111

    申请日：2014-12-26

    Applicant: Southeast University

    Inventor： Weiwei Shan ,  Longxing Shi ,  Jun Yang

    IPC: G01R31/28 ,  H03K3/03

    Abstract: A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

    Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT
    8.
    发明授权
    Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT 有权

    公开(公告)号：US11651766B2

    公开(公告)日：2023-05-16

    申请号：US17181908

    申请日：2021-02-22

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei Shan ,  Lixuan Zhu ,  Jun Yang ,  Longxing Shi

    IPC: G10L15/02 ,  G06F17/14 ,  G10L25/24

    CPC classification number: G10L15/02 ,  G06F17/142 ,  G10L25/24

    Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

    High energy efficiency switched-capacitor power converter
    9.
    发明授权
    High energy efficiency switched-capacitor power converter 有权

    公开(公告)号：US11290009B2

    公开(公告)日：2022-03-29

    申请号：US16966474

    申请日：2020-04-30

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Chao Chen ,  Jun Yang ,  Xinning Liu

    IPC: H02M3/07 ,  H02M1/00

    Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.

    Circuit for enhancing robustness of sub-threshold SRAM memory cell
    10.
    发明授权
    Circuit for enhancing robustness of sub-threshold SRAM memory cell 有权
    用于增强子阈值SRAM存储单元鲁棒性的电路

    公开(公告)号：US09236115B2

    公开(公告)日：2016-01-12

    申请号：US14369651

    申请日：2012-12-27

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

    IPC: G11C11/419 ,  G11C11/417 ,  H01L27/11 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

    Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

    Abstract translation: 用于提高子阈值SRAM存储单元的工艺稳健性的电路用作子阈值SRAM存储单元的辅助电路。 电路的输出端连接到子阈值SRAM存储单元的PMOS晶体管和电路中PMOS晶体管的衬底。 该电路包括用于PMOS晶体管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS和NMOS晶体管的阈值电压波动，以自适应的方式改变子阈值SRAM存储单元中的PMOS晶体管的衬底电压和电路中的PMOS晶体管，从而调节阈值 PMOS晶体管的电压，使得PMOS和NMOS晶体管的阈值电压匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限和子阈值SRAM存储单元的工艺稳健性。

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