公开(公告)号：US20120031476A1

公开(公告)日：2012-02-09

申请号：US12849966

申请日：2010-08-04

申请人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L31/0352 ,  H01L31/18

CPC分类号： H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

摘要翻译： 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US08653360B2

公开(公告)日：2014-02-18

申请号：US12849966

申请日：2010-08-04

申请人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

摘要： A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

摘要翻译： 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US20100221867A1

公开(公告)日：2010-09-02

申请号：US12436249

申请日：2009-05-06

申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

IPC分类号： H01L31/0376 ,  H01L21/762

CPC分类号： H01L31/03921 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02667 ,  H01L21/7624 ,  H01L21/76245 ,  H01L21/76262 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

摘要： A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.

摘要翻译： 提供了一种用于制造SOI衬底的损耗成本方法。 该方法包括通过利用蒸发沉积工艺在衬底的半导体区域上形成一层p型掺杂的非晶态含Si层。 然后进行固相重结晶步骤，以将叠层内的非晶态含硅层转化为p型掺杂单晶含Si层的堆叠。 重结晶后，对单晶含Si层进行阳极氧化和至少氧化步骤以形成SOI衬底。 太阳能电池和/或其他半导体器件可以形成在本发明的SOI衬底的上表面上。

公开(公告)号：US20120037998A1

公开(公告)日：2012-02-16

申请号：US12855738

申请日：2010-08-13

申请人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L27/092 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

摘要翻译： 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

公开(公告)号：US08354694B2

公开(公告)日：2013-01-15

申请号：US12855738

申请日：2010-08-13

申请人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

摘要翻译： 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

公开(公告)号：US08298923B2

公开(公告)日：2012-10-30

申请号：US12912940

申请日：2010-10-27

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。

公开(公告)号：US20120104390A1

公开(公告)日：2012-05-03

申请号：US12912940

申请日：2010-10-27

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/04 ,  H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。

公开(公告)号：US08933456B2

公开(公告)日：2015-01-13

申请号：US13616322

申请日：2012-09-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/38 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。

公开(公告)号：US08866227B2

公开(公告)日：2014-10-21

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/77 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。

公开(公告)号：US20130099319A1

公开(公告)日：2013-04-25

申请号：US13607743

申请日：2012-09-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/77 ,  H01L21/823412 ,  H01L27/092

摘要： A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，其可以从提供半导体衬底开始，所述半导体衬底包括与掩埋电介质层直接接触的包含硅层的第一器件区域，包括与所述掩埋电介质层直接接触的硅锗层的第二器件区域 以及掺杂有碳层的硅的第三器件区域。 然后可以在半导体衬底的第一器件区域内的硅层上形成至少一个低功率半导体器件。 可以在半导体衬底的第二器件区域的硅锗层上形成至少一个p型半导体器件。 可以在半导体衬底的第三器件区域的掺杂有碳层的硅上形成至少一个n型半导体器件。