公开(公告)号：US08422270B2

公开(公告)日：2013-04-16

申请号：US13044892

申请日：2011-03-10

申请人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US20110228586A1

公开(公告)日：2011-09-22

申请号：US13044892

申请日：2011-03-10

申请人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US08482956B2

公开(公告)日：2013-07-09

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US20120014163A1

公开(公告)日：2012-01-19

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US20100232209A1

公开(公告)日：2010-09-16

申请号：US12722851

申请日：2010-03-12

申请人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

发明人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/24

摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

摘要翻译： 非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。 非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。 形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成， 要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线 检测到。

公开(公告)号：US08120944B2

公开(公告)日：2012-02-21

申请号：US12722851

申请日：2010-03-12

申请人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

发明人： Suguru Kawabata ,  Kazuya Ishihara ,  Yoshiji Ohta

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/24

摘要： A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected.

摘要翻译： 非易失性半导体存储器件可以在存储单元的非易失性可变电阻元件上同时进行形成处理，并且使形成时间更短。 非易失性半导体存储器件具有设置在存储单元阵列和第二选择线（位线））解码器之间的形成检测电路。 形成检测电路通过测量当通过第二选择线同时施加用于形成处理的电压脉冲时第二选择线的电位的波动或流过第二选择线的电流来检测存储单元的形成处理的完成， 要在其上执行形成处理的存储单元连接到相同的第一选择线（字线），并且防止电压施加到连接到形成处理完成的存储单元的第二选择线 检测到。

公开(公告)号：US08450713B2

公开(公告)日：2013-05-28

申请号：US12713223

申请日：2010-02-26

申请人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

发明人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

IPC分类号： H01L45/00 ,  H01L21/822

CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616

摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

摘要翻译： 具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

公开(公告)号：US20100219392A1

公开(公告)日：2010-09-02

申请号：US12713223

申请日：2010-02-26

申请人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

发明人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

IPC分类号： H01L45/00 ,  H01L21/822

CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616

摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

摘要翻译： 具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

公开(公告)号：US20100118592A1

公开(公告)日：2010-05-13

申请号：US12611279

申请日：2009-11-03

申请人： Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

发明人： Kazuya Ishihara ,  Yutaka Ishikawa ,  Yoshiji Ohta

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2216/22

摘要： Provided is a nonvolatile semiconductor memory device capable of performing a writing action for a memory cell at high speed. The device comprises: a memory cell array having a first sub-bank and a second sub-bank each having a plurality of nonvolatile memory cells arranged in a form of a matrix; a row decoder shared by the first sub-bank and the second sub-bank; a first column decoder and a second column decoder provided in the first sub-bank and the second sub-bank, respectively; and a control circuit arranged to execute alternately a first action cycle to perform a programming action in the first sub-bank and a reading action for a programming verifying action in the second sub-bank and a second action cycle to perform the reading action for the programming verifying action in the first sub-bank and the programming action in the second sub-bank.

摘要翻译： 提供了一种能够高速地对存储单元执行写入动作的非易失性半导体存储器件。 该装置包括：具有第一子库和第二子库的存储单元阵列，每个具有以矩阵形式布置的多个非易失性存储单元; 由第一子银行和第二子银行共享的行解码器; 分别设置在第一子行和第二子行中的第一列解码器和第二列解码器; 以及控制电路，被配置为交替地执行第一动作循环以在第一子存储体中执行编程动作，以及执行用于第二子存储体中的编程验证动作的读取动作和第二动作循环，以执行对于第二子存储体的读取动作 在第一子行中编程验证动作和第二子行中的编程动作。

公开(公告)号：US08400830B2

公开(公告)日：2013-03-19

申请号：US13131388

申请日：2009-11-18

申请人： Yutaka Ishikawa ,  Kazuya Ishihara ,  Yoshiji Ohta

发明人： Yutaka Ishikawa ,  Kazuya Ishihara ,  Yoshiji Ohta

IPC分类号： G11C11/34

CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/79

摘要： A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.

摘要翻译： 一种非易失性半导体存储器件，其中可以延长存储器单元寿命，同时使得可以以位为单位执行写入。 当命令信息表示写入时，比较单元37将目标存储器单元中的写入数据与写入目标数据进行比较，以便在写入/读取控制单元40给出比较结果时，当比较结果表示匹配时，写入/读取控制单元40 不指示解码器单元（51A，51B和53）在目标存储单元中执行写入，并且当比较结果表示不匹配时，写入/读取控制单元40指示解码器单元将写入目标数据写入到 目标存储单元