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公开(公告)号：US20140210556A1
公开(公告)日：2014-07-31
申请号：US14150219
申请日：2014-01-08
Applicant: TDK CORPORATION
Inventor： Tomohiko SHIBUYA , Atsushi AJIOKA , Sadaharu Yoneda , Atsushi TSUMITA
IPC: H03F3/193
CPC classification number: H03F3/193 , H03F1/0266 , H03F2200/408
Abstract: Since a high-frequency signal that is output from a high-frequency oscillator circuit section is detected in a detector circuit and a bias of a negative voltage is supplied from a bias circuit section to the high-frequency amplifier circuit section with a detection voltage that is detected, a negative power supply circuit such as a DC/DC converter or a peripheral circuit is not required, and since a negative bias voltage can be supplied to a high-frequency amplifier circuit, downsizing can be achieved with a low cost.
Abstract translation: 由于在检测器电路中检测到从高频振荡电路部分输出的高频信号，并且从偏置电路部分向高频放大器电路部分提供负电压的偏压，检测电压为 ，则不需要诸如DC / DC转换器或外围电路的负电源电路，并且由于可以向高频放大器电路提供负偏压，因此可以以低成本实现小型化。
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公开(公告)号：US20130257540A1
公开(公告)日：2013-10-03
申请号：US13852159
申请日：2013-03-28
Applicant: TDK CORPORATION
Inventor： Tomihiko SHIBUYA , Atsushi AJIOKA , Atsushi TSUMITA
IPC: H03F3/19
CPC classification number: H03F3/19 , H01L23/66 , H01L2924/0002 , H01L2924/00
Abstract: A high frequency amplifier is characterized wherein a power amplification element and at least one of temperature compensation elements are adjacently provided on a first semiconductor layer, a first wiring pattern connected to the power amplification element, a second wiring pattern connected to the temperature compensation element, and a ground electrode are provided on at least one of second semiconductor layers existing in layers different from the first semiconductor layer, and the ground electrode is formed on the second semiconductor layer corresponding to a region that substantially projects a crevice part on which the temperature compensation element and the power amplification element are provided, on the same plane as the first semiconductor element.
Abstract translation: 一种高频放大器，其特征在于，功率放大元件和温度补偿元件中的至少一个相邻地设置在第一半导体层上，连接到功率放大元件的第一布线图案，连接到温度补偿元件的第二布线图案， 并且在与第一半导体层不同的层中存在的第二半导体层中的至少一个上设置接地电极，并且在第二半导体层上形成接地电极，所述第二半导体层对应于基本上突出有温度补偿的缝隙部分的区域 元件和功率放大元件设置在与第一半导体元件相同的平面上。
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公开(公告)号：US20210399211A1
公开(公告)日：2021-12-23
申请号：US17288612
申请日：2019-03-28
Applicant: TDK CORPORATION
Inventor： Atsushi TSUMITA , Yohei SHIOKAWA
Abstract: A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring that extends in a second direction different from the first direction and together with the nonmagnetic layer sandwiches the first ferromagnetic layer in the first direction; and an electrode that together with the nonmagnetic layer sandwiches the second ferromagnetic layer in at least a part in the first direction, wherein the electrode is in contact with at least a part of a lateral side surface of the second ferromagnetic layer.
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4.发明申请公开(公告)号：US20200312392A1
公开(公告)日：2020-10-01
申请号：US16829188
申请日：2020-03-25
Applicant: TDK CORPORATION
Inventor： Atsushi TSUMITA , Yohei SHIOKAWA , Eiji KOMURA
IPC: G11C11/16 , H01L43/10 , H01L43/12 , H01L43/08 , H01L27/11597
Abstract: A storage element includes a first ferromagnetic layer; a second ferromagnetic layer; a nonmagnetic layer that is sandwiched between the first ferromagnetic layer and the second ferromagnetic layer in a first direction; a first wiring which extends in a second direction different from the first direction, and the first wiring being configured to sandwich the first ferromagnetic layer with the nonmagnetic layer in the first direction; an electrode which sandwiches the second ferromagnetic layer at least partially with the nonmagnetic layer in the first direction; and a compound part which is positioned inside the electrode and has a lower thermal conductivity than the electrode.
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公开(公告)号：US20150180419A1
公开(公告)日：2015-06-25
申请号：US14571929
申请日：2014-12-16
Applicant: TDK CORPORATION
Inventor： Tomohiko SHIBUYA , Atsushi AJIOKA , Atsushi TSUMITA , Sadaharu YONEDA
CPC classification number: H03F3/193 , H03F3/195 , H03F3/211 , H03F3/245 , H03F2200/451 , H03F2203/21106 , H03F2203/21142
Abstract: There is provided a high-frequency amplifier including a divider, a plurality of amplifiers for amplifying a high-frequency signal distributed by the divider and outputting the amplified high-frequency signal, a combiner for combining amplified high-frequency signals, a base substrate, a conductor pattern that is connected to a ground end of each of the amplifiers, and a ground electrode. Each of the conductor patterns has a first conductive portion. A slot is disposed between the two conductor patterns connected to the corresponding adjacent amplifiers. Between the adjacent amplifiers, two vias are formed so that the slot is sandwiched between the vias. One of the two conductor patterns is connected to the ground electrode via one of the two vias, and the other one of the conductor patterns is connected to the ground electrode via the other one of the two vias.
Abstract translation: 提供了一种高频放大器，包括分频器，用于放大由分频器分配的高频信号并输出放大的高频信号的多个放大器，用于组合放大的高频信号的组合器，基底衬底， 连接到每个放大器的接地端的导体图案和接地电极。 每个导体图案具有第一导电部分。 在连接到相应的相邻放大器的两个导体图案之间设置槽。 在相邻的放大器之间，形成两个通孔，使得狭槽夹在通孔之间。 两个导体图案中的一个通过两个通孔中的一个连接到接地电极，另一个导体图案经由两个通孔中的另一个连接到接地电极。
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Patent Agency Ranking
公开(公告)号：US20230189663A1
公开(公告)日：2023-06-15
申请号：US18103818
申请日：2023-01-31
Applicant: TDK CORPORATION
Inventor： Tomoyuki SASAKI , Yohei SHIOKAWA , Atsushi TSUMITA
CPC classification number: H10N52/80 , G11C11/18 , H10B61/22 , H10N50/10 , H10N50/85 , H10N52/01 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
Abstract: A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element, a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines.
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公开(公告)号：US20210184105A1
公开(公告)日：2021-06-17
申请号：US17269173
申请日：2019-02-01
Applicant: TDK CORPORATION
Inventor： Tomoyuki SASAKI , Atsushi TSUMITA , Yohei SHIOKAWA
Abstract: A spin-orbit torque magnetoresistance effect element includes an element part including a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, a spin-orbit torque wiring positioned in a first direction with respect to the element part, facing the first ferromagnetic layer of the element part, and extending in a second direction, a first conductive part and a second conductive part facing the spin-orbit torque wiring at positions sandwiching the element part when viewed from the first direction, and a gate part including a gate insulating layer and a gate electrode in order from a position near the spin-orbit torque wiring, in which the spin-orbit torque wiring includes a semiconductor to which a scattering element is added.
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公开(公告)号：US20210159397A1
公开(公告)日：2021-05-27
申请号：US17165309
申请日：2021-02-02
Applicant: TDK CORPORATION
Inventor： Tomoyuki SASAKI , Yohei SHIOKAWA , Atsushi TSUMITA
Abstract: A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element; a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines.
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公开(公告)号：US20190189909A1
公开(公告)日：2019-06-20
申请号：US16271112
申请日：2019-02-08
Applicant: TDK CORPORATION
Inventor： Tomoyuki SASAKI , Yohei SHIOKAWA , Atsushi TSUMITA
CPC classification number: H01L43/04 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/18 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/14
Abstract: A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element; a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines.
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公开(公告)号：US20210364580A1
公开(公告)日：2021-11-25
申请号：US16475478
申请日：2018-12-25
Applicant: TDK CORPORATION
Inventor： Atsushi TSUMITA , Tomoyuki SASAKI
Abstract: A spin element includes an element portion including a first ferromagnetic layer, a conducting portion that extends in a first direction as viewed in a lamination direction of the first ferromagnetic layer and faces the first ferromagnetic layer, and a current path extending from the conducting portion to a semiconductor circuit and having a resistance adjusting portion between the conducting portion and the semiconductor circuit, wherein the resistance value of the resistance adjusting portion is higher than the resistance value of the conducting portion, and the temperature coefficient of the volume resistivity of a material forming the resistance adjusting portion is lower than the temperature coefficient of the volume resistivity of a material forming the conducting portion.
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