公开(公告)号：US20240363465A1

公开(公告)日：2024-10-31

申请号：US18309546

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Daiki Komatsu ,  Hau Nguyen

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/78 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L21/568 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/05558 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48245 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/05442 ,  H01L2924/0695 ,  H01L2924/07025

Abstract: An electronic device includes a semiconductor die, a die attach pad, an adhesive, a conductive lead, and a package structure, where the semiconductor die has opposite first and second sides, a conductive terminal on the second side, and an electrical isolation coating layer that extends on the first side, the adhesive adheres the first side of the semiconductor die to the die attach pad, the conductive lead is electrically coupled to the conductive terminal of the semiconductor die, and the package structure encloses at least a portion of the semiconductor die.

公开(公告)号：US11955456B2

公开(公告)日：2024-04-09

申请号：US17364735

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Hau Nguyen ,  Kurt Edward Sincerbox ,  Makoto Shibuya

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/97 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

公开(公告)号：US20230317568A1

公开(公告)日：2023-10-05

申请号：US17710077

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Daiki Komatsu ,  Anindya Poddar ,  Hau Nguyen

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L21/56 ,  H01L21/78 ,  H01L2224/32245 ,  H01L2224/2919 ,  H01L2224/48221 ,  H01L2224/73265 ,  H01L2224/92247

Abstract: An integrated circuit package includes a die attach pad (DAP) having a top surface and a layer of insulating material applied to the top surface of the DAP. A silicon-on-insulator (SOI) device is mounted on the insulating material using a die attach paste or film. A plurality of leads are coupled to the SOI device using bond wires. A mold compound covers at least a portion of the DAP and the SOI device. The insulating material may be polyimide or polyamide-imide that has been inkjet printed or screen printed on the DAP. The insulating material may be a parylene material that is applied to the top surface of the DAP using chemical vapor deposition. The insulating material has a thickness of 1-25 um and has a breakdown voltage of approximately 250V/um.

公开(公告)号：US11450638B2

公开(公告)日：2022-09-20

申请号：US17009648

申请日：2020-09-01

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US11417579B2

公开(公告)日：2022-08-16

申请号：US16996742

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

公开(公告)号：US11302615B2

公开(公告)日：2022-04-12

申请号：US16840407

申请日：2020-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

公开(公告)号：US10763231B2

公开(公告)日：2020-09-01

申请号：US16047888

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10650957B1

公开(公告)日：2020-05-12

申请号：US16176630

申请日：2018-10-31

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar

IPC: H01F27/26 ,  H01F27/40 ,  H01L23/495 ,  H01L23/00 ,  H01F27/28 ,  H01F41/24 ,  H01L23/66 ,  H01L23/31

Abstract: Apparatus to form a transformer, an inductor, a capacitor or other passive electronic component, with patterned conductive features in a lamination structure, and one or more ferrite sheets or other magnetic core structures attached to the lamination structure via one or more inkjet printed magnetic adhesive layers that join the magnetic core structure or structures to the lamination structure.

公开(公告)号：US20200091048A1

公开(公告)日：2020-03-19

申请号：US16134924

申请日：2018-09-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L23/532 ,  H01L21/48

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US20200075441A1

公开(公告)日：2020-03-05

申请号：US16120922

申请日：2018-09-04

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.