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    Power transistor coupled to multiple sense transistors
    1.
    发明授权
    Power transistor coupled to multiple sense transistors 有权

    公开(公告)号：US10679938B2

    公开(公告)日：2020-06-09

    申请号：US16050383

    申请日：2018-07-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kuntal Joardar ,  Min Chu ,  Vijay Krishnamurthy ,  Tikno Harjono ,  Ankur Chauhan ,  Vinayak Hegde ,  Manish Srivastava

    IPC: G11C17/00 ,  H01L23/525 ,  G11C17/16 ,  H01L27/112

    Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.

    METHODS AND APPARATUS TO PREVENT UNDESIRED TRIGGERING OF SHORT CIRCUIT OR OVER CURRENT PROTECTION
    2.
    发明申请
    METHODS AND APPARATUS TO PREVENT UNDESIRED TRIGGERING OF SHORT CIRCUIT OR OVER CURRENT PROTECTION 审中-公开

    公开(公告)号：US20200028345A1

    公开(公告)日：2020-01-23

    申请号：US16428493

    申请日：2019-05-31

    Applicant: Texas Instruments Incorporated

    Inventor： Subrato Roy ,  Ankur Chauhan ,  Vishal Gupta

    IPC: H02H1/04 ,  H02H1/00 ,  H02H3/28 ,  H02H7/20

    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

    Controlling current limits in current limiting circuits
    3.
    发明授权
    Controlling current limits in current limiting circuits 有权

    公开(公告)号：US10348280B2

    公开(公告)日：2019-07-09

    申请号：US15857135

    申请日：2017-12-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ankur Chauhan ,  Subrato Roy

    IPC: G01R19/00 ,  G01R1/30 ,  H02H5/04 ,  G05F1/00 ,  G05F3/16 ,  G01K3/10 ,  H03K5/08 ,  G05F1/46 ,  G05F1/573

    Abstract: An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

    Configurable retry for system operations
    6.
    发明授权
    Configurable retry for system operations 有权

    公开(公告)号：US10541525B1

    公开(公告)日：2020-01-21

    申请号：US16287458

    申请日：2019-02-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Abhrarup Barman Roy ,  Abhishek Kumar ,  Subrato Roy ,  Ankur Chauhan ,  Abhinay Patil

    IPC: G06F13/20 ,  G06F13/24 ,  H02H3/06 ,  H03K5/135 ,  H03K21/10 ,  H03K21/38 ,  H03K19/20

    Abstract: The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.

    Current sensing and control for a transistor power switch
    7.
    发明授权
    Current sensing and control for a transistor power switch 有权

    公开(公告)号：US10361695B2

    公开(公告)日：2019-07-23

    申请号：US16001518

    申请日：2018-06-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ankur Chauhan ,  Sudheer Prasad ,  Md. Abidur Rahman ,  Subrato Roy

    IPC: H03K3/00 ,  H03K17/082 ,  G01R19/00 ,  H01L23/525 ,  H03K17/687

    Abstract: An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

    Multi-segment FET gate enhancement detection
    9.
    发明授权
    Multi-segment FET gate enhancement detection 有权

    公开(公告)号：US11977403B2

    公开(公告)日：2024-05-07

    申请号：US18090861

    申请日：2022-12-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Vinayak Hegde ,  Rolly Baradiya ,  Ankur Chauhan

    IPC: G05F1/26 ,  G05F1/46 ,  G05F1/56 ,  G05F3/26

    CPC classification number: G05F1/561 ,  G05F1/468 ,  G05F3/262

    Abstract: In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.

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