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公开(公告)号：US20170187515A1
公开(公告)日：2017-06-29
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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公开(公告)号：US20180091157A1
公开(公告)日：2018-03-29
申请号：US15715151
申请日：2017-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Theertham Srinivas , Jagdish Chand Goyal , Peeyoosh Mirajkar
CPC classification number: H03L7/087 , H03L7/193 , H03L7/1974 , H03L7/1976 , H03L2207/10
Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.
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公开(公告)号：US09509323B2
公开(公告)日：2016-11-29
申请号：US14709759
申请日：2015-05-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Krishnaswamy Thiagarajan , Jagdish Chand Goyal , Srikanth Manian , Debapriya Sahu
CPC classification number: H03L7/1976 , H03L7/0814 , H03L7/1974 , H03L2207/10 , H04B1/40 , H04L7/033 , H04L7/0331
Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
Abstract translation: 一个抑制整数边界杂散的分数N频率合成器。 频率合成器包括分数N锁相环（PLL）和参考频率缩放器。 参考频率缩放器耦合到PLL的参考时钟输入，参考频率缩放器包括可编程分频器和与可编程分频器串联连接的可编程倍频器。 分频器和乘法器中的每一个被配置为通过可编程整数值来缩放提供给PLL的参考频率。
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4.发明授权公开(公告)号：US09407424B1
公开(公告)日：2016-08-02
申请号：US14682249
申请日：2015-04-09
Applicant: Texas Instruments Incorporated
Inventor： Bharathi Rahuldev Holla , Jagdish Chand Goyal , Biman Chattopadhyay , Sujoy Chakravarty , Sumantra Seth
IPC: H04L7/00
CPC classification number: H04L7/0337 , H04L7/0004
Abstract: A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.
Abstract translation: 时钟和数据恢复模块（CDR）被配置为使用每个单位间隔（UI）仅使用两个采样来执行快速锁定。 从多个时钟相位信号中选择两个时钟相位信号。 响应于两个时钟相位信号，以每个UI两倍的速率对数据比特序列进行采样，其中将每个UI的第一样本指定为边缘样本，将第二样本指定为数据样本。 通过将每个边缘样本与下一个数据样本进行比较，与数据比特序列的相关数据转换相比，每个边缘样本被提前/晚选。 采样时钟被锁定，使得边缘采样在数据转换附近发生，通过响应于早/晚表决反复调整两个所选择的时钟相位信号的相位可变步长。
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公开(公告)号：US10243573B1
公开(公告)日：2019-03-26
申请号：US15959332
申请日：2018-04-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jagdish Chand Goyal , Peeyoosh Mirajkar , Shankaranarayana Karantha , Ashwin Ravisankar , Srikanth Manian , Srinivas Theertham
Abstract: Frequency synthesis is based on phase synchronizing PLL output across REFERENCE and VCO clock domains (including outputs for multiple PLLs), based on an input (REF-Domain) SYNC signal (phase timing reference). A frequency synthesizer includes a VCO to generate VCO_clk and a PLL output circuit, such as a channel divider, to generate PLL_OUT based on VCO_clk (in the VCO-Domain). The VCO loop includes a PD to phase compare an input PD_clock based on REF_CLK, and a VCO feedback signal based on divided VCO_clk (NDIV_out). SYNC alignment circuitry generates a SYNC alignment signal based on SYNC, PD_clk, and NDIV_out (REF-Domain), which is used to synchronize the PLL output circuit and PLL_OUT to SYNC. If a reference divider generates PD_clk, the SYNC alignment circuitry generates a reset to SYNC-align the reference divider. If the VCO loop uses fractional divide, the SYNC alignment circuitry resets the fractional modulator to a known sequence.
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Patent Agency Ranking
公开(公告)号：US09503105B2
公开(公告)日：2016-11-22
申请号：US14868785
申请日：2015-09-29
Applicant: Texas Instruments Incorporated
Inventor： Peeyoosh Nitin Mirajkar , Jagdish Chand Goyal , Sankaran Aniruddhan
CPC classification number: H03L7/095 , H03L7/089 , H03L7/1072 , H03L7/1077
Abstract: Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
Abstract translation: 所描述的示例包括控制锁相环（PLL）或其他锁定电路的锁定时间的电路和方法，其中相位频率检测器（PFD）电路从第一模式切换以向电荷泵提供控制输入信号作为 脉冲信号具有对应于参考时钟信号和反馈时钟信号之间的相位差的脉冲宽度到第二模式，以响应于检测到的周期滑移条件将控制输入信号保持在恒定值一段预定时间以增强环路 在频率转换期间过滤电流，以减少锁定电路的锁定时间。
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公开(公告)号：US10439620B2
公开(公告)日：2019-10-08
申请号：US15715151
申请日：2017-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Theertham Srinivas , Jagdish Chand Goyal , Peeyoosh Mirajkar
Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.
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公开(公告)号：US09954705B2
公开(公告)日：2018-04-24
申请号：US15388407
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Srikanth Manian , Srinivas Theertham , Jagdish Chand Goyal , Robert Karl Butler
CPC classification number: H04L27/261 , H03L7/099 , H03L7/1976
Abstract: The disclosure provides a frequency synthesizer. It includes a PFD that generates an up signal and a down signal in response to a reference signal and a feedback signal. A charge pump generates a control voltage in response to the up signal and the down signal. A low pass filter generates a filtered voltage in response to the control voltage. An oscillator circuit generates an output signal in response to the filtered voltage. A feedback divider is coupled between the oscillator circuit and the PFD, and divides the output signal by a first integer divider to generate the feedback signal. A sigma delta modulator (SDM) generates a second integer divider in response to the feedback signal, the reference signal, the output signal and the first integer divider. A digital filter is coupled between the SDM and the feedback divider, and filters quantization noise associated with the SDM.
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公开(公告)号：US09948312B2
公开(公告)日：2018-04-17
申请号：US15443217
申请日：2017-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03L7/087 , H03L7/0895 , H03L7/1072 , H03L7/113
Abstract: A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump.
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10.发明授权公开(公告)号：US09667300B2
公开(公告)日：2017-05-30
申请号：US14753940
申请日：2015-06-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H04B1/40 , H03L7/1075 , H03L7/1976
Abstract: A frequency synthesizer that includes a reference frequency scaler and a phase locked loop (PLL) coupled to the reference frequency scaler. The reference frequency scaler is configured to generate a first reference frequency and a second reference frequency. The PLL is configured to generate a first output frequency based on the first reference frequency during a first timeslot and a second output frequency based on the second reference frequency during a second timeslot. The PLL comprises a loop filter that includes a first switch connected in series to a first capacitor and configured to close during the first timeslot and a second switch connected in series to a second capacitor and configured to open during the first timeslot.
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