公开(公告)号：US20250013518A1

公开(公告)日：2025-01-09

申请号：US18892677

申请日：2024-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/07 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F11/27 ,  G06F11/30 ,  G06F11/36 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/16

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US20240320094A1

公开(公告)日：2024-09-26

申请号：US18674108

申请日：2024-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F11/1076 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3891 ,  G06F11/00 ,  G06F11/1405 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30043 ,  G06F9/30141 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3881 ,  G06F11/10 ,  G06F13/38 ,  G06F13/40 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20240231827A1

公开(公告)日：2024-07-11

申请号：US18614947

申请日：2024-03-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Son H. Tran

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3004 ,  G06F9/3013 ,  G06F9/35 ,  G06F9/3851

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

公开(公告)号：US20240134800A1

公开(公告)日：2024-04-25

申请号：US18401824

申请日：2024-01-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0875 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F12/0897

CPC classification number: G06F12/0875 ,  G06F9/30003 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3867 ,  G06F12/0897 ,  G06F11/10

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0′s in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

公开(公告)号：US11714646B2

公开(公告)日：2023-08-01

申请号：US17163639

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F12/0875 ,  G06F9/32

CPC classification number: G06F9/30065 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/34 ,  G06F9/3016 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3802 ,  G06F12/0875

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

公开(公告)号：US11709779B2

公开(公告)日：2023-07-25

申请号：US17067986

申请日：2020-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak

IPC: G06F12/0897 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0862 ,  G06F12/04 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/355

CPC classification number: G06F12/0897 ,  G06F9/3001 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3887 ,  G06F12/04 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/3552 ,  G06F2212/1056 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor may specify a fixed read-only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US11604652B2

公开(公告)日：2023-03-14

申请号：US17164448

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Sahithi Krishna ,  Soujanya Narnur

IPC: G06F7/76 ,  G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US11573847B2

公开(公告)日：2023-02-07

申请号：US16988500

申请日：2020-08-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/36 ,  G06F11/10

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US20230004391A1

公开(公告)日：2023-01-05

申请号：US17897405

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/30 ,  G06F9/34 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F13/14

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.

公开(公告)号：US20210357219A1

公开(公告)日：2021-11-18

申请号：US17391143

申请日：2021-08-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are reduced by restricting read access. Dedicated predicate registers reduce requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.