公开(公告)号：US09899794B2

公开(公告)日：2018-02-20

申请号：US14319696

申请日：2014-06-30

Applicant: Texas Instruments Incorporated

Inventor： Will Kiang Wong ,  Roozbeh Parsa ,  William French ,  Noboru Nakanishi

IPC: H01L31/0232 ,  H01S5/022 ,  H01L31/0203 ,  H01L31/02 ,  H01L31/167 ,  H01L31/173 ,  H01S5/183

CPC classification number: H01S5/02276 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/167 ,  H01L31/173 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/16152 ,  H01S5/005 ,  H01S5/02208 ,  H01S5/02248 ,  H01S5/02252 ,  H01S5/0683 ,  H01S5/183 ,  H01L2924/00014

Abstract: A optoelectronic package includes an inner package with a dielectric substrate having at least a first dielectric level with a photodetector (PD) die on a die attach area, first routing connecting a first contact to a first external bond pad (FEBP), and second routing connecting a second contact to a second external bond pad (SEBP). An outer package (OP) includes a ceramic substrate including a light source die on a base portion in direct line of sight with the PD including a first electrode and second electrode. A first wire bond connects the FEBP to a first terminal, a second wire bond connects the SEBP to a second terminal, a third wire bond connects the first electrode to a third terminal, and a fourth wire bond connects the second electrode to a fourth terminal.

公开(公告)号：US11574855B2

公开(公告)日：2023-02-07

申请号：US17399018

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Noboru Nakanishi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

公开(公告)号：US20160347607A1

公开(公告)日：2016-12-01

申请号：US14723122

申请日：2015-05-27

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  G01N27/02 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Abstract translation: 一种集成电路（“IC”）封装，包括具有顶表面和底表面的IC管芯，具有相对的第一和第二端部的中间部分的细长元件。 中间部分位于IC芯片顶表面附近。 IC封装还包括具有顶表面，底表面和相对的第一和第二横向侧表面的密封剂块。 密封剂块封装IC芯片和细长构件。 细长构件的第一和第二端部中的任一个或两个都被暴露。

公开(公告)号：US20210375730A1

公开(公告)日：2021-12-02

申请号：US17399018

申请日：2021-08-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Noboru Nakanishi

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

公开(公告)号：US10077186B2

公开(公告)日：2018-09-18

申请号：US15603183

申请日：2017-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  B81C1/00 ,  G01N33/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

公开(公告)号：US20160068387A1

公开(公告)日：2016-03-10

申请号：US14480658

申请日：2014-09-09

Applicant: Texas Instruments Incorporated

Inventor： Noboru Nakanishi

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/0023 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged device (100) with a semiconductor chip (101) with a MEMS device (102) in the central chip area, wherein the package includes a light-sensitive first (150) and an opaque second (160) polymerized compound. The second compound (160) encapsulates the chip peripheral areas with the terminals (103) and wire bonds (130), and forms a sidewall (160a, diameter 112) around the un-encapsulated central area. The first compound (150) continues from the sidewall inward as a frame (inner diameter 110) around the un-encapsulated central area.

Abstract translation: 一种具有在中心芯片区域中具有MEMS器件（102）的半导体芯片（101）的封装器件（100），其中所述封装包括感光的第一（150）和不透明的第二（160）聚合化合物。 第二化合物（160）利用端子（103）和引线接合（130）封装芯片外围区域，并且在未封装的中心区域周围形成侧壁（160a，直径112）。 第一化合物（150）从侧壁向内延伸为围绕未包封的中心区域的框架（内径110）。

公开(公告)号：US08993412B1

公开(公告)日：2015-03-31

申请号：US14098018

申请日：2013-12-05

Applicant: Texas Instruments Incorporated

Inventor： Shoichi Iriguchi ,  Noboru Nakanishi

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/3043 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a dicing tape and an anchoring material. The anchoring material and the wafer are cut with the sawing blade. During the cutting operation, the anchoring material reduces backside chipping of the die and eliminates fly-away die. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.

Abstract translation: 在本发明的一个方面，将描述锯切半导体晶片的方法。 半导体晶片定位在晶片锯切装置中，其包括物理地支撑半导体晶片的锯切刀片和可动支撑结构。 半导体晶片与具有各种层的支撑结构耦合，包括切割带和锚固材料。 用锯刀切割锚定材料和晶片。 在切割操作期间，锚固材料减少了模具的背面碎裂并且消除了飞离模具。 本发明的各个方面涉及包括上述锯切方法的布置和晶片锯切装置。

公开(公告)号：US11088055B2

公开(公告)日：2021-08-10

申请号：US16221291

申请日：2018-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Noboru Nakanishi

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

公开(公告)号：US20170253476A1

公开(公告)日：2017-09-07

申请号：US15603183

申请日：2017-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B7/00 ,  G01N33/00 ,  H01L23/16 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

公开(公告)号：US09688530B2

公开(公告)日：2017-06-27

申请号：US14723122

申请日：2015-05-27

Applicant: Texas Instruments Incorporated

Inventor： Makoto Shibuya ,  Luu Nguyen ,  Noboru Nakanishi

IPC: B81B1/00 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0038 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/098 ,  B81C1/00285 ,  B81C2203/0154 ,  G01N33/0009 ,  H01L23/16 ,  H01L23/3121 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.